;; Machine description for AArch64 architecture. ;; Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ;; Contributed by ARM Ltd. ;; ;; This file is part of GCC. ;; ;; GCC is free software; you can redistribute it and/or modify it ;; under the terms of the GNU General Public License as published by ;; the Free Software Foundation; either version 3, or (at your option) ;; any later version. ;; ;; GCC is distributed in the hope that it will be useful, but ;; WITHOUT ANY WARRANTY; without even the implied warranty of ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ;; General Public License for more details. ;; ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING3. If not see ;; http://www.gnu.org/licenses/.
;; ------------------------------------------------------------------- ;; Mode Iterators ;; -------------------------------------------------------------------
;; Iterator for General Purpose Integer registers (32- and 64-bit modes) (define_mode_iterator GPI [SI DI])
;; Iterator for QI and HI modes (define_mode_iterator SHORT [QI HI])
;; Iterator for all integer modes (up to 64-bit) (define_mode_iterator ALLI [QI HI SI DI])
;; Iterator scalar modes (up to 64-bit) (define_mode_iterator SDQ_I [QI HI SI DI])
;; Iterator for all integer modes that can be extended (up to 64-bit) (define_mode_iterator ALLX [QI HI SI])
;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes) (define_mode_iterator GPF [SF DF])
;; Integer vector modes. (define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
;; Integer vector modes. (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
;; vector and scalar, 64 & 128-bit container, all integer modes (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
;; vector and scalar, 64 & 128-bit container: all vector integer modes; ;; 64-bit scalar integer mode (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
;; Double vector modes. (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
;; vector, 64-bit container, all integer modes (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
;; Quad vector modes. (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
;; All vector modes, except double. (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
;; Vector and scalar, 64 & 128-bit container: all vector integer mode; ;; 8, 16, 32-bit scalar integer modes (define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI])
;; Vector modes for moves. (define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
;; This mode iterator allows :PTR to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator PTR [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; Vector Float modes. (define_mode_iterator VDQF [V2SF V4SF V2DF])
;; Vector Float modes with 2 elements. (define_mode_iterator V2F [V2SF V2DF])
;; All modes. (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
;; Vector modes for Integer reduction across lanes. (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI])
;; All double integer narrow-able modes. (define_mode_iterator VDN [V4HI V2SI DI])
;; All quad integer narrow-able modes. (define_mode_iterator VQN [V8HI V4SI V2DI])
;; All double integer widen-able modes. (define_mode_iterator VDW [V8QI V4HI V2SI])
;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
;; All quad integer widen-able modes. (define_mode_iterator VQW [V16QI V8HI V4SI])
;; Double vector modes for combines. (define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
;; Double vector modes. (define_mode_iterator VD_RE [V8QI V4HI V2SI DI DF V2SF])
;; Vector modes except double int. (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
;; Vector modes for H and S types. (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
;; Vector and scalar integer modes for H and S (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
;; Vector and scalar 64-bit container: 16, 32-bit integer modes (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
;; Vector 64-bit container: 16, 32-bit integer modes (define_mode_iterator VD_HSI [V4HI V2SI])
;; Scalar 64-bit container: 16, 32-bit integer modes (define_mode_iterator SD_HSI [HI SI])
;; Vector 64-bit container: 16, 32-bit integer modes (define_mode_iterator VQ_HSI [V8HI V4SI])
;; All byte modes. (define_mode_iterator VB [V8QI V16QI])
(define_mode_iterator TX [TI TF])
;; ------------------------------------------------------------------ ;; Unspec enumerations for Advance SIMD. These could well go into ;; aarch64.md but for their use in int_iterators here. ;; ------------------------------------------------------------------
(define_c_enum "unspec" [ UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md. UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md. UNSPEC_FMAXV ; Used in aarch64-simd.md. UNSPEC_FMINV ; Used in aarch64-simd.md. UNSPEC_FADDV ; Used in aarch64-simd.md. UNSPEC_ADDV ; Used in aarch64-simd.md. UNSPEC_SMAXV ; Used in aarch64-simd.md. UNSPEC_SMINV ; Used in aarch64-simd.md. UNSPEC_UMAXV ; Used in aarch64-simd.md. UNSPEC_UMINV ; Used in aarch64-simd.md. UNSPEC_SHADD ; Used in aarch64-simd.md. UNSPEC_UHADD ; Used in aarch64-simd.md. UNSPEC_SRHADD ; Used in aarch64-simd.md. UNSPEC_URHADD ; Used in aarch64-simd.md. UNSPEC_SHSUB ; Used in aarch64-simd.md. UNSPEC_UHSUB ; Used in aarch64-simd.md. UNSPEC_SRHSUB ; Used in aarch64-simd.md. UNSPEC_URHSUB ; Used in aarch64-simd.md. UNSPEC_ADDHN ; Used in aarch64-simd.md. UNSPEC_RADDHN ; Used in aarch64-simd.md. UNSPEC_SUBHN ; Used in aarch64-simd.md. UNSPEC_RSUBHN ; Used in aarch64-simd.md. UNSPEC_ADDHN2 ; Used in aarch64-simd.md. UNSPEC_RADDHN2 ; Used in aarch64-simd.md. UNSPEC_SUBHN2 ; Used in aarch64-simd.md. UNSPEC_RSUBHN2 ; Used in aarch64-simd.md. UNSPEC_SQDMULH ; Used in aarch64-simd.md. UNSPEC_SQRDMULH ; Used in aarch64-simd.md. UNSPEC_PMUL ; Used in aarch64-simd.md. UNSPEC_USQADD ; Used in aarch64-simd.md. UNSPEC_SUQADD ; Used in aarch64-simd.md. UNSPEC_SQXTUN ; Used in aarch64-simd.md. UNSPEC_SQXTN ; Used in aarch64-simd.md. UNSPEC_UQXTN ; Used in aarch64-simd.md. UNSPEC_SSRA ; Used in aarch64-simd.md. UNSPEC_USRA ; Used in aarch64-simd.md. UNSPEC_SRSRA ; Used in aarch64-simd.md. UNSPEC_URSRA ; Used in aarch64-simd.md. UNSPEC_SRSHR ; Used in aarch64-simd.md. UNSPEC_URSHR ; Used in aarch64-simd.md. UNSPEC_SQSHLU ; Used in aarch64-simd.md. UNSPEC_SQSHL ; Used in aarch64-simd.md. UNSPEC_UQSHL ; Used in aarch64-simd.md. UNSPEC_SQSHRUN ; Used in aarch64-simd.md. UNSPEC_SQRSHRUN ; Used in aarch64-simd.md. UNSPEC_SQSHRN ; Used in aarch64-simd.md. UNSPEC_UQSHRN ; Used in aarch64-simd.md. UNSPEC_SQRSHRN ; Used in aarch64-simd.md. UNSPEC_UQRSHRN ; Used in aarch64-simd.md. UNSPEC_SSHL ; Used in aarch64-simd.md. UNSPEC_USHL ; Used in aarch64-simd.md. UNSPEC_SRSHL ; Used in aarch64-simd.md. UNSPEC_URSHL ; Used in aarch64-simd.md. UNSPEC_SQRSHL ; Used in aarch64-simd.md. UNSPEC_UQRSHL ; Used in aarch64-simd.md. UNSPEC_CMEQ ; Used in aarch64-simd.md. UNSPEC_CMLE ; Used in aarch64-simd.md. UNSPEC_CMLT ; Used in aarch64-simd.md. UNSPEC_CMGE ; Used in aarch64-simd.md. UNSPEC_CMGT ; Used in aarch64-simd.md. UNSPEC_CMHS ; Used in aarch64-simd.md. UNSPEC_CMHI ; Used in aarch64-simd.md. UNSPEC_SSLI ; Used in aarch64-simd.md. UNSPEC_USLI ; Used in aarch64-simd.md. UNSPEC_SSRI ; Used in aarch64-simd.md. UNSPEC_USRI ; Used in aarch64-simd.md. UNSPEC_SSHLL ; Used in aarch64-simd.md. UNSPEC_USHLL ; Used in aarch64-simd.md. UNSPEC_ADDP ; Used in aarch64-simd.md. UNSPEC_CMTST ; Used in aarch64-simd.md. UNSPEC_FMAX ; Used in aarch64-simd.md. UNSPEC_FMIN ; Used in aarch64-simd.md. ])
;; ------------------------------------------------------------------- ;; Mode attributes ;; -------------------------------------------------------------------
;; In GPI templates, a string like "%0" will expand to "%w0" in the ;; 32-bit version and "%x0" in the 64-bit version. (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
;; For scalar usage of vector/FP registers (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d") (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") (V2DI "") (V2SF "") (V4SF "") (V2DF "")])
;; For scalar usage of vector/FP registers, narrowing (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s") (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") (V2DI "") (V2SF "") (V4SF "") (V2DF "")])
;; For scalar usage of vector/FP registers, widening (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d") (V8QI "") (V16QI "") (V4HI "") (V8HI "") (V2SI "") (V4SI "") (V2DI "") (V2SF "") (V4SF "") (V2DF "")])
;; Map a floating point mode to the appropriate register name prefix (define_mode_attr s [(SF "s") (DF "d")])
;; Give the length suffix letter for a sign- or zero-extension. (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
;; Give the number of bits in the mode (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
;; Give the ordinal of the MSB in the mode (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
;; Attribute to describe constants acceptable in logical operations (define_mode_attr lconst [(SI "K") (DI "L")])
;; Map a mode to a specific constraint character. (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
(define_mode_attr Vtype [(V8QI "8b") (V16QI "16b") (V4HI "4h") (V8HI "8h") (V2SI "2s") (V4SI "4s") (V2DI "2d") (V2SF "2s") (V4SF "4s") (V2DF "2d")])
(define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b") (V4HI ".4h") (V8HI ".8h") (V2SI ".2s") (V4SI ".4s") (V2DI ".2d") (V2SF ".2s") (V4SF ".4s") (V2DF ".2d") (DI "") (SI "") (HI "") (QI "") (TI "")])
;; Register suffix narrowed modes for VQN. (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h") (V2DI ".2s") (DI "") (SI "") (HI "")])
;; Mode-to-individual element type mapping. (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (V4HI "h") (V8HI "h") (V2SI "s") (V4SI "s") (V2DI "d") (V2SF "s") (V4SF "s") (V2DF "d") (QI "b") (HI "h") (SI "s") (DI "d")])
;; Mode-to-bitwise operation type mapping. (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b") (V4HI "8b") (V8HI "16b") (V2SI "8b") (V4SI "16b") (V2DI "16b") (V2SF "8b") (V4SF "16b") (V2DF "16b")])
;; Define element mode for each vector mode. (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (V4HI "HI") (V8HI "HI") (V2SI "SI") (V4SI "SI") (DI "DI") (V2DI "DI") (V2SF "SF") (V4SF "SF") (V2DF "DF") (SI "SI") (HI "HI") (QI "QI")])
;; Define container mode for lane selection. (define_mode_attr VCON [(V8QI "V16QI") (V16QI "V16QI") (V4HI "V8HI") (V8HI "V8HI") (V2SI "V4SI") (V4SI "V4SI") (DI "V2DI") (V2DI "V2DI") (V2SF "V2SF") (V4SF "V4SF") (V2DF "V2DF") (SI "V4SI") (HI "V8HI") (QI "V16QI")])
;; Half modes of all vector modes. (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI") (V4HI "V2HI") (V8HI "V4HI") (V2SI "SI") (V4SI "V2SI") (V2DI "DI") (V2SF "SF") (V4SF "V2SF") (V2DF "DF")])
;; Double modes of vector modes. (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI") (V2SI "V4SI") (V2SF "V4SF") (SI "V2SI") (DI "V2DI") (DF "V2DF")])
;; Double modes of vector modes (lower case). (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi") (V2SI "v4si") (V2SF "v4sf") (SI "v2si") (DI "v2di")])
;; Narrowed modes for VDN. (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI") (DI "V2SI")])
;; Narrowed double-modes for VQN (Used for XTN). (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI") (DI "SI") (SI "HI") (HI "QI")])
;; Narrowed quad-modes for VQN (Used for XTN2). (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI") (V2DI "V4SI")])
;; Register suffix narrowed modes for VQN. (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h") (V2DI "2s")])
;; Register suffix narrowed modes for VQN. (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h") (V2DI "4s")])
;; Widened modes of vector modes. (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI") (V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") (HI "SI") (SI "DI")]
)
;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") (V2SI "2d") (V16QI "8h") (V8HI "4s") (V4SI "2d")])
;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") (V2SI ".2d") (V16QI ".8h") (V8HI ".4s") (V4SI ".2d") (SI "") (HI "")])
;; Lower part register suffixes for VQW. (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") (V4SI "2s")])
;; Define corresponding core/FP element mode for each vector mode. (define_mode_attr vw [(V8QI "w") (V16QI "w") (V4HI "w") (V8HI "w") (V2SI "w") (V4SI "w") (DI "x") (V2DI "x") (V2SF "s") (V4SF "s") (V2DF "d")])
;; Double vector types for ALLX. (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
;; Mode of result of comparison operations. (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") (V4HI "V4HI") (V8HI "V8HI") (V2SI "V2SI") (V4SI "V4SI") (V2SF "V2SI") (V4SF "V4SI") (DI "DI") (V2DI "V2DI")])
;; Vm for lane instructions is restricted to FP_LO_REGS. (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x") (V2SI "w") (V4SI "w") (SI "w")])
;; ------------------------------------------------------------------- ;; Code Iterators ;; -------------------------------------------------------------------
;; This code iterator allows the various shifts supported on the core (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
;; This code iterator allows the shifts supported in arithmetic instructions (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
;; Code iterator for logical operations (define_code_iterator LOGICAL [and ior xor])
;; Code iterator for sign/zero extension (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
;; All division operations (signed/unsigned) (define_code_iterator ANY_DIV [div udiv])
;; Code iterator for sign/zero extraction (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
;; Code iterator for equality comparisons (define_code_iterator EQL [eq ne])
;; Code iterator for less-than and greater/equal-to (define_code_iterator LTGE [lt ge])
;; Iterator for _sync operations that where the operation can be ;; represented directly RTL. This is all of the sync operations bar ;; nand. (define_code_iterator syncop [plus minus ior xor and])
;; Iterator for integer conversions (define_code_iterator FIXUORS [fix unsigned_fix])
;; Code iterator for variants of vector max and min. (define_code_iterator MAXMIN [smax smin umax umin])
;; Code iterator for variants of vector max and min. (define_code_iterator ADDSUB [plus minus])
;; Code iterator for variants of vector saturating binary ops. (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
;; Code iterator for variants of vector saturating unary ops. (define_code_iterator UNQOPS [ss_neg ss_abs])
;; Code iterator for signed variants of vector saturating binary ops. (define_code_iterator SBINQOPS [ss_plus ss_minus])
;; ------------------------------------------------------------------- ;; Code Attributes ;; ------------------------------------------------------------------- ;; Map rtl objects to optab names (define_code_attr optab [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr") (rotatert "rotr") (sign_extend "extend") (zero_extend "zero_extend") (sign_extract "extv") (zero_extract "extzv") (and "and") (ior "ior") (xor "xor") (not "one_cmpl") (neg "neg") (plus "add") (minus "sub") (ss_plus "qadd") (us_plus "qadd") (ss_minus "qsub") (us_minus "qsub") (ss_neg "qneg") (ss_abs "qabs") (eq "eq") (ne "ne") (lt "lt") (ge "ge")])
;; Optab prefix for sign/zero-extending operations (define_code_attr su_optab [(sign_extend "") (zero_extend "u") (div "") (udiv "u") (fix "") (unsigned_fix "u") (ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")])
;; Similar for the instruction mnemonics (define_code_attr shift [(ashift "lsl") (ashiftrt "asr") (lshiftrt "lsr") (rotatert "ror")])
;; Map shift operators onto underlying bit-field instructions (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx") (lshiftrt "ubfx") (rotatert "extr")])
;; Logical operator instruction mnemonics (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
;; Similar, but when not(op) (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
;; Sign- or zero-extending load (define_code_attr ldrxt [(sign_extend "ldrs") (zero_extend "ldr")])
;; Sign- or zero-extending data-op (define_code_attr su [(sign_extend "s") (zero_extend "u") (sign_extract "s") (zero_extract "u") (fix "s") (unsigned_fix "u") (div "s") (udiv "u")])
;; Emit cbz/cbnz depending on comparison type. (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
;; Emit tbz/tbnz depending on comparison type. (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
;; Max/min attributes. (define_code_attr maxmin [(smax "smax") (smin "smin") (umax "umax") (umin "umin")])
;; MLA/MLS attributes. (define_code_attr as [(ss_plus "a") (ss_minus "s")])
;; ------------------------------------------------------------------- ;; Int Iterators. ;; ------------------------------------------------------------------- (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV UNSPEC_SMAXV UNSPEC_SMINV])
(define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV])
(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD UNSPEC_SRHADD UNSPEC_URHADD UNSPEC_SHSUB UNSPEC_UHSUB UNSPEC_SRHSUB UNSPEC_URHSUB])
(define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN UNSPEC_SUBHN UNSPEC_RSUBHN])
(define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
(define_int_iterator FMAXMIN [UNSPEC_FMAX UNSPEC_FMIN])
(define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
(define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
(define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
(define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL UNSPEC_SRSHL UNSPEC_URSHL])
(define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
(define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL UNSPEC_SQRSHL UNSPEC_UQRSHL])
(define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA UNSPEC_SRSRA UNSPEC_URSRA])
(define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI UNSPEC_SSRI UNSPEC_USRI])
(define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
(define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
(define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN UNSPEC_SQSHRN UNSPEC_UQSHRN UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
(define_int_iterator VCMP_S [UNSPEC_CMEQ UNSPEC_CMGE UNSPEC_CMGT UNSPEC_CMLE UNSPEC_CMLT])
(define_int_iterator VCMP_U [UNSPEC_CMHS UNSPEC_CMHI UNSPEC_CMTST])
;; ------------------------------------------------------------------- ;; Int Iterators Attributes. ;; ------------------------------------------------------------------- (define_int_attr maxminv [(UNSPEC_UMAXV "umax") (UNSPEC_UMINV "umin") (UNSPEC_SMAXV "smax") (UNSPEC_SMINV "smin")])
(define_int_attr fmaxminv [(UNSPEC_FMAXV "max") (UNSPEC_FMINV "min")])
(define_int_attr fmaxmin [(UNSPEC_FMAX "fmax") (UNSPEC_FMIN "fmin")])
(define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u") (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur") (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u") (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur") (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r") (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r") (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r") (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r") (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u") (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su") (UNSPEC_SSLI "s") (UNSPEC_USLI "u") (UNSPEC_SSRI "s") (UNSPEC_USRI "u") (UNSPEC_USRA "u") (UNSPEC_SSRA "s") (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr") (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr") (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s") (UNSPEC_UQSHL "u") (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s") (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u") (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u") (UNSPEC_USHL "u") (UNSPEC_SSHL "s") (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s") (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr") (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s") ])
(define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r") (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r") (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r") ])
(define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l") (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
(define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "") (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u") (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "") (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
(define_int_attr addsub [(UNSPEC_SHADD "add") (UNSPEC_UHADD "add") (UNSPEC_SRHADD "add") (UNSPEC_URHADD "add") (UNSPEC_SHSUB "sub") (UNSPEC_UHSUB "sub") (UNSPEC_SRHSUB "sub") (UNSPEC_URHSUB "sub") (UNSPEC_ADDHN "add") (UNSPEC_SUBHN "sub") (UNSPEC_RADDHN "add") (UNSPEC_RSUBHN "sub") (UNSPEC_ADDHN2 "add") (UNSPEC_SUBHN2 "sub") (UNSPEC_RADDHN2 "add") (UNSPEC_RSUBHN2 "sub")])
(define_int_attr cmp [(UNSPEC_CMGE "ge") (UNSPEC_CMGT "gt") (UNSPEC_CMLE "le") (UNSPEC_CMLT "lt") (UNSPEC_CMEQ "eq") (UNSPEC_CMHS "hs") (UNSPEC_CMHI "hi") (UNSPEC_CMTST "tst")])
(define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")])