target-mips: FRE support, MSA & R6 fixes
This commit includes cherry-picked commits
from the PRPL & upstream foundation QEMU.
List of squashed commits from PRPL foundation QEMU:
0dec08a target-mips: add mips32r6-generic CPU
9e721de target-mips: Correct the handling of writes to CP0.Status for MIPSr6
902b883 target-mips: fix hflags modified in delay / forbidden slot
db1ab66 target-mips: fix cpu_mips_validate_access()
3f4046b target-mips: add Config5.FRE support
dfa9fa8 target-mips: fix to clear msacsr
fe96cf5 target-mips: Misaligned Memory Accesses for MSA
bc5a035 target-mips: Misaligned Memory Accesses for R6
f2cf59e softmmu: Add size argument to do_unaligned_access()
List of squashed commits from upstream QEMU:
0af7a37 target-mips: save cpu state before calling MSA load and store helpers
Change-Id: I28775e28995ce414b3d78d208cf7bb0bb5efd343
15 files changed