Snap for 6439596 from 2493ca265742b83a11531856451849ccf8c27f9f to qt-aml-tzdata-release
Change-Id: I5c1d71dd14b0897cd7c9162bc985375275cd65fa
diff --git a/.gitignore b/.gitignore
index 811348a..d51e619 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,6 @@
+bsd-core/*/@
+bsd-core/*/machine
+*~
*.1
*.3
*.5
@@ -14,22 +17,17 @@
*.o.cmd
*.sw?
*.trs
-*~
-.*check*
-.*install*
.depend
.deps
.libs
.tmp_versions
-/_build*
-/build*
+.*check*
+.*install*
Makefile
Makefile.in
TAGS
aclocal.m4
autom4te.cache
-bsd-core/*/@
-bsd-core/*/machine
build-aux
bus_if.h
compile
@@ -49,22 +47,21 @@
export_syms
i915.kld
install-sh
-libdrm.pc
libdrm/config.h.in
-libdrm_amdgpu.pc
-libdrm_etnaviv.pc
-libdrm_exynos.pc
-libdrm_freedreno.pc
+libdrm.pc
libdrm_intel.pc
libdrm_nouveau.pc
-libdrm_omap.pc
libdrm_radeon.pc
+libdrm_omap.pc
+libdrm_exynos.pc
+libdrm_freedreno.pc
+libdrm_amdgpu.pc
libdrm_vc4.pc
+libdrm_etnaviv.pc
libkms.pc
libtool
ltmain.sh
mach64.kld
-man/*.3
man/.man_fixup
mga.kld
missing
@@ -77,34 +74,35 @@
sis.kld
stamp-h1
tdfx.kld
-tests/amdgpu/amdgpu_test
+via.kld
tests/auth
+tests/amdgpu/amdgpu_test
tests/dristat
tests/drmdevice
tests/drmsl
tests/drmstat
-tests/etnaviv/etnaviv_2d_test
-tests/etnaviv/etnaviv_bo_cache_test
-tests/etnaviv/etnaviv_cmd_stream_test
-tests/exynos/exynos_fimg2d_event
-tests/exynos/exynos_fimg2d_perf
-tests/exynos/exynos_fimg2d_test
tests/getclient
tests/getstats
tests/getversion
tests/hash
-tests/kms/kms-steal-crtc
-tests/kms/kms-universal-planes
-tests/kmstest/kmstest
tests/lock
-tests/modeprint/modeprint
-tests/modetest/modetest
-tests/name_from_fd
tests/openclose
-tests/proptest/proptest
-tests/radeon/radeon_ttm
tests/random
tests/setversion
tests/updatedraw
+tests/modeprint/modeprint
+tests/modetest/modetest
+tests/name_from_fd
+tests/proptest/proptest
+tests/kms/kms-steal-crtc
+tests/kms/kms-universal-planes
+tests/kmstest/kmstest
tests/vbltest/vbltest
-via.kld
+tests/radeon/radeon_ttm
+tests/exynos/exynos_fimg2d_event
+tests/exynos/exynos_fimg2d_perf
+tests/exynos/exynos_fimg2d_test
+tests/etnaviv/etnaviv_2d_test
+tests/etnaviv/etnaviv_cmd_stream_test
+tests/etnaviv/etnaviv_bo_cache_test
+man/*.3
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
deleted file mode 100644
index ac2a9d2..0000000
--- a/.gitlab-ci.yml
+++ /dev/null
@@ -1,159 +0,0 @@
-.artifacts-meson: &artifacts-meson
- when: always
- paths:
- - _build/meson-logs
-
-.artifacts-autotools: &artifacts-autotools
- when: always
- paths:
- - _build/*.log
- - _build/*/*.log
- - _build/*/*/*.log
-
-.meson-build: &meson-build
- - meson _build
- -D amdgpu=true
- -D cairo-tests=true
- -D etnaviv=true
- -D exynos=true
- -D freedreno=true
- -D freedreno-kgsl=true
- -D intel=true
- -D libkms=true
- -D man-pages=true
- -D nouveau=true
- -D omap=true
- -D radeon=true
- -D tegra=true
- -D udev=true
- -D valgrind=true
- -D vc4=true
- -D vmwgfx=true
- - ninja -C _build
- - ninja -C _build test
-
-.autotools-build: &autotools-build
- - mkdir _build
- - cd _build
- - ../autogen.sh
- --enable-udev
- --enable-libkms
- --enable-intel
- --enable-radeon
- --enable-amdgpu
- --enable-nouveau
- --enable-vmwgfx
- --enable-omap-experimental-api
- --enable-exynos-experimental-api
- --enable-freedreno
- --enable-freedreno-kgsl
- --enable-tegra-experimental-api
- --enable-vc4
- --enable-etnaviv-experimental-api
- - make
- - make check
-
-latest-meson:
- stage: build
- image: archlinux/base:latest
- before_script:
- - pacman -Syu --noconfirm --needed
- base-devel
- meson
- libpciaccess
- libxslt docbook-xsl
- valgrind
- libatomic_ops
- cairo cunit
- script: *meson-build
-
-latest-autotools:
- stage: build
- image: archlinux/base:latest
- artifacts: *artifacts-autotools
- before_script:
- - pacman -Syu --noconfirm --needed
- base-devel
- libpciaccess
- libxslt docbook-xsl
- valgrind
- libatomic_ops
- cairo cunit
- xorg-util-macros
- git # autogen.sh depends on git
- script: *autotools-build
-
-oldest-meson:
- stage: build
- image: debian:stable
- artifacts: *artifacts-meson
- before_script:
- - printf > /etc/dpkg/dpkg.cfg.d/99-exclude-cruft "%s\n"
- 'path-exclude=/usr/share/doc/*'
- 'path-exclude=/usr/share/man/*'
- - printf > /usr/sbin/policy-rc.d "%s\n"
- '#!/bin/sh'
- 'exit 101'
- - chmod +x /usr/sbin/policy-rc.d
- - apt-get update
- - apt-get -y --no-install-recommends install
- build-essential
- pkg-config
- xsltproc
- libxslt1-dev docbook-xsl
- valgrind
- libatomic-ops-dev
- libcairo2-dev libcunit1-dev
- ninja-build
- python3 python3-pip
- wget
- # We need `--no-check-certificate` here because Debian's CA list is
- # too old to know about LetsEncrypt's CA, so it refuses to connect
- # to FreeDesktop.org
- - LIBPCIACCESS_VERSION=libpciaccess-0.10 &&
- wget --no-check-certificate https://xorg.freedesktop.org/releases/individual/lib/$LIBPCIACCESS_VERSION.tar.bz2 &&
- tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2 &&
- (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make install)
- - pip3 install wheel setuptools
- - pip3 install meson==0.43
- - export PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
- - export LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
- script: *meson-build
-
-oldest-autotools:
- stage: build
- image: debian:stable
- artifacts: *artifacts-autotools
- before_script:
- - printf > /etc/dpkg/dpkg.cfg.d/99-exclude-cruft "%s\n"
- 'path-exclude=/usr/share/doc/*'
- 'path-exclude=/usr/share/man/*'
- - printf > /usr/sbin/policy-rc.d "%s\n"
- '#!/bin/sh'
- 'exit 101'
- - chmod +x /usr/sbin/policy-rc.d
- - apt-get update
- - apt-get -y --no-install-recommends install
- build-essential
- automake
- autoconf
- libtool
- pkg-config
- xsltproc
- libxslt1-dev docbook-xsl
- valgrind
- libatomic-ops-dev
- libcairo2-dev libcunit1-dev
- wget
- xutils-dev
- git # autogen.sh depends on git
- # We need `--no-check-certificate` here because Debian's CA list is
- # too old to know about LetsEncrypt's CA, so it refuses to connect
- # to FreeDesktop.org
- - LIBPCIACCESS_VERSION=libpciaccess-0.10 &&
- wget --no-check-certificate https://xorg.freedesktop.org/releases/individual/lib/$LIBPCIACCESS_VERSION.tar.bz2 &&
- tar -jxvf $LIBPCIACCESS_VERSION.tar.bz2 &&
- (cd $LIBPCIACCESS_VERSION && ./configure --prefix=$HOME/prefix && make install)
- - export PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
- - export LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
- script: *autotools-build
diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst
deleted file mode 100644
index 96f1e4f..0000000
--- a/CONTRIBUTING.rst
+++ /dev/null
@@ -1,105 +0,0 @@
-Contributing to libdrm
-======================
-
-Submitting Patches
-------------------
-
-Patches should be sent to dri-devel@lists.freedesktop.org, using git
-send-email. For patches only touching driver specific code one of the driver
-mailing lists (like amd-gfx@lists.freedesktop.org) is also appropriate. See git
-documentation for help:
-
-http://git-scm.com/documentation
-
-Since dri-devel is a very busy mailing list please use --subject-prefix="PATCH
-libdrm" to make it easier to find libdrm patches. This is best done by running
-
- git config --local format.subjectprefix "PATCH libdrm"
-
-The first line of a commit message should contain a prefix indicating what part
-is affected by the patch followed by one sentence that describes the change. For
-examples:
-
- amdgpu: Use uint32_t i in amdgpu_find_bo_by_cpu_mapping
-
-The body of the commit message should describe what the patch changes and why,
-and also note any particular side effects. For a recommended reading on
-writing commit messages, see:
-
-http://who-t.blogspot.de/2009/12/on-commit-messages.html
-
-Your patches should also include a Signed-off-by line with your name and email
-address. If you're not the patch's original author, you should also gather
-S-o-b's by them (and/or whomever gave the patch to you.) The significance of
-this is that it certifies that you created the patch, that it was created under
-an appropriate open source license, or provided to you under those terms. This
-lets us indicate a chain of responsibility for the copyright status of the code.
-For more details:
-
-https://developercertificate.org/
-
-We won't reject patches that lack S-o-b, but it is strongly recommended.
-
-Review and Merging
-------------------
-
-Patches should have at least one positive review (Reviewed-by: tag) or
-indication of approval (Acked-by: tag) before merging. For any code shared
-between drivers this is mandatory.
-
-Please note that kernel/userspace API header files have special rules, see
-include/drm/README.
-
-Coding style in the project loosely follows the CodingStyle of the linux kernel:
-
-https://www.kernel.org/doc/html/latest/process/coding-style.html?highlight=coding%20style
-
-Commit Rights
--------------
-
-Commit rights will be granted to anyone who requests them and fulfills the
-below criteria:
-
-- Submitted a few (5-10 as a rule of thumb) non-trivial (not just simple
- spelling fixes and whitespace adjustment) patches that have been merged
- already. Since libdrm is just a glue library between the kernel and userspace
- drivers, merged patches to those components also count towards the commit
- criteria.
-
-- Are actively participating on discussions about their work (on the mailing
- list or IRC). This should not be interpreted as a requirement to review other
- peoples patches but just make sure that patch submission isn't one-way
- communication. Cross-review is still highly encouraged.
-
-- Will be regularly contributing further patches. This includes regular
- contributors to other parts of the open source graphics stack who only
- do the oddball rare patch within libdrm itself.
-
-- Agrees to use their commit rights in accordance with the documented merge
- criteria, tools, and processes.
-
-To apply for commit rights ("Developer" role in gitlab) send a mail to
-dri-devel@lists.freedesktop.org and please ping the maintainers if your request
-is stuck.
-
-Committers are encouraged to request their commit rights get removed when they
-no longer contribute to the project. Commit rights will be reinstated when they
-come back to the project.
-
-Maintainers and committers should encourage contributors to request commit
-rights, as especially junior contributors tend to underestimate their skills.
-
-Code of Conduct
----------------
-
-Please be aware the fd.o Code of Conduct also applies to libdrm:
-
-https://www.freedesktop.org/wiki/CodeOfConduct/
-
-See the gitlab project owners for contact details of the libdrm maintainers.
-
-Abuse of commit rights, like engaging in commit fights or willfully pushing
-patches that violate the documented merge criteria, will also be handled through
-the Code of Conduct enforcement process.
-
-Happy hacking!
diff --git a/Makefile.am b/Makefile.am
index 730de1f..6de5677 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -96,6 +96,10 @@
endif
endif
+if HAVE_ROCKCHIP
+ROCKCHIP_SUBDIR = rockchip
+endif
+
SUBDIRS = \
. \
$(LIBKMS_SUBDIR) \
@@ -111,7 +115,8 @@
$(ETNAVIV_SUBDIR) \
data \
tests \
- $(MAN_SUBDIR)
+ $(MAN_SUBDIR) \
+ $(ROCKCHIP_SUBDIR)
libdrm_la_LTLIBRARIES = libdrm.la
libdrm_ladir = $(libdir)
@@ -121,7 +126,6 @@
libdrm_la_CPPFLAGS = -I$(top_srcdir)/include/drm
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
$(VALGRIND_CFLAGS)
libdrm_la_SOURCES = $(LIBDRM_FILES)
diff --git a/Makefile.sources b/Makefile.sources
index 55290fe..1f8372b 100644
--- a/Makefile.sources
+++ b/Makefile.sources
@@ -25,7 +25,6 @@
include/drm/i915_drm.h \
include/drm/mach64_drm.h \
include/drm/mga_drm.h \
- include/drm/msm_drm.h \
include/drm/nouveau_drm.h \
include/drm/qxl_drm.h \
include/drm/r128_drm.h \
diff --git a/OWNERS b/OWNERS
index 7b4c82d..9f1c88b 100644
--- a/OWNERS
+++ b/OWNERS
@@ -1,5 +1,5 @@
# Default code reviewers picked from top 3 or more developers.
# Please update this list if you find better candidates.
-adelva@google.com
+astrachan@google.com
john.stultz@linaro.org
seanpaul@google.com
diff --git a/README.rst b/README
similarity index 67%
rename from README.rst
rename to README
index e47cb24..f3df9ac 100644
--- a/README.rst
+++ b/README
@@ -1,17 +1,15 @@
libdrm - userspace library for drm
-----------------------------------
-This is libdrm, a userspace library for accessing the DRM, direct rendering
-manager, on Linux, BSD and other operating systems that support the ioctl
-interface.
-The library provides wrapper functions for the ioctls to avoid exposing the
-kernel interface directly, and for chipsets with drm memory manager, support
-for tracking relocations and buffers.
-New functionality in the kernel DRM drivers typically requires a new libdrm,
-but a new libdrm will always work with an older kernel.
-
-libdrm is a low-level library, typically used by graphics drivers such as
-the Mesa drivers, the X drivers, libva and similar projects.
+This is libdrm, a userspace library for accessing the DRM, direct
+rendering manager, on Linux, BSD and other operating systems that
+support the ioctl interface. The library provides wrapper functions
+for the ioctls to avoid exposing the kernel interface directly, and
+for chipsets with drm memory manager, support for tracking relocations
+and buffers. libdrm is a low-level library, typically used by
+graphics drivers such as the Mesa DRI drivers, the X drivers, libva
+and similar projects. New functionality in the kernel DRM drivers
+typically requires a new libdrm, but a new libdrm will always work
+with an older kernel.
Compiling
diff --git a/amdgpu/Android.sources.bp b/amdgpu/Android.sources.bp
index be85283..ed85682 100644
--- a/amdgpu/Android.sources.bp
+++ b/amdgpu/Android.sources.bp
@@ -10,6 +10,7 @@
"amdgpu_gpu_info.c",
"amdgpu_vamgr.c",
"amdgpu_vm.c",
- "handle_table.c",
+ "util_hash.c",
+ "util_hash_table.c",
],
}
diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index ef8ab05..a1b0d05 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -26,7 +26,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
@@ -48,6 +47,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_amdgpu.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = amdgpu-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources
index d6df324..498b64c 100644
--- a/amdgpu/Makefile.sources
+++ b/amdgpu/Makefile.sources
@@ -7,8 +7,10 @@
amdgpu_internal.h \
amdgpu_vamgr.c \
amdgpu_vm.c \
- handle_table.c \
- handle_table.h
+ util_hash.c \
+ util_hash.h \
+ util_hash_table.c \
+ util_hash_table.h
LIBDRM_AMDGPU_H_FILES := \
amdgpu.h
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 5ce15f4..90b7a1d 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.am/libdrm_amdgpuinclude_HEADERS
@@ -18,9 +16,6 @@
amdgpu_bo_export
amdgpu_bo_free
amdgpu_bo_import
-amdgpu_bo_inc_ref
-amdgpu_bo_list_create_raw
-amdgpu_bo_list_destroy_raw
amdgpu_bo_list_create
amdgpu_bo_list_destroy
amdgpu_bo_list_update
@@ -38,7 +33,6 @@
amdgpu_cs_ctx_create
amdgpu_cs_ctx_create2
amdgpu_cs_ctx_free
-amdgpu_cs_ctx_override_priority
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
@@ -50,23 +44,15 @@
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
-amdgpu_cs_submit_raw2
amdgpu_cs_syncobj_export_sync_file
-amdgpu_cs_syncobj_export_sync_file2
amdgpu_cs_syncobj_import_sync_file
-amdgpu_cs_syncobj_import_sync_file2
-amdgpu_cs_syncobj_query
amdgpu_cs_syncobj_reset
amdgpu_cs_syncobj_signal
-amdgpu_cs_syncobj_timeline_signal
-amdgpu_cs_syncobj_timeline_wait
-amdgpu_cs_syncobj_transfer
amdgpu_cs_syncobj_wait
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
amdgpu_device_initialize
-amdgpu_find_bo_by_cpu_mapping
amdgpu_get_marketing_name
amdgpu_query_buffer_size_alignment
amdgpu_query_crtc_from_id
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 66e45f7..36f9105 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -42,7 +42,6 @@
#endif
struct drm_amdgpu_info_hw_ip;
-struct drm_amdgpu_bo_list_entry;
/*--------------------------------------------------------------------------*/
/* --------------------------- Defines ------------------------------------ */
@@ -85,12 +84,7 @@
amdgpu_bo_handle_type_kms = 1,
/** DMA-buf fd handle */
- amdgpu_bo_handle_type_dma_buf_fd = 2,
-
- /** Deprecated in favour of and same behaviour as
- * amdgpu_bo_handle_type_kms, use that instead of this
- */
- amdgpu_bo_handle_type_kms_noimport = 3,
+ amdgpu_bo_handle_type_dma_buf_fd = 2
};
/** Define known types of GPU VM VA ranges */
@@ -679,30 +673,7 @@
amdgpu_bo_handle *buf_handle);
/**
- * Validate if the user memory comes from BO
- *
- * \param dev - [in] Device handle. See #amdgpu_device_initialize()
- * \param cpu - [in] CPU address of user allocated memory which we
- * want to map to GPU address space (make GPU accessible)
- * (This address must be correctly aligned).
- * \param size - [in] Size of allocation (must be correctly aligned)
- * \param buf_handle - [out] Buffer handle for the userptr memory
- * if the user memory is not from BO, the buf_handle will be NULL.
- * \param offset_in_bo - [out] offset in this BO for this user memory
- *
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
-*/
-int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- amdgpu_bo_handle *buf_handle,
- uint64_t *offset_in_bo);
-
-/**
- * Free previously allocated memory
+ * Free previosuly allocated memory
*
* \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
* \param buf_handle - \c [in] Buffer handle to free
@@ -722,16 +693,6 @@
int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
/**
- * Increase the reference count of a buffer object
- *
- * \param bo - \c [in] Buffer object handle to increase the reference count
- *
- * \sa amdgpu_bo_alloc(), amdgpu_bo_free()
- *
-*/
-void amdgpu_bo_inc_ref(amdgpu_bo_handle bo);
-
-/**
* Request CPU access to GPU accessible memory
*
* \param buf_handle - \c [in] Buffer handle
@@ -780,37 +741,6 @@
*
* \param dev - \c [in] Device handle.
* See #amdgpu_device_initialize()
- * \param number_of_buffers - \c [in] Number of BOs in the list
- * \param buffers - \c [in] List of BO handles
- * \param result - \c [out] Created BO list handle
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2()
-*/
-int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
- uint32_t number_of_buffers,
- struct drm_amdgpu_bo_list_entry *buffers,
- uint32_t *result);
-
-/**
- * Destroys a BO list handle.
- *
- * \param bo_list - \c [in] BO list handle.
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2()
-*/
-int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list);
-
-/**
- * Creates a BO list handle for command submission.
- *
- * \param dev - \c [in] Device handle.
- * See #amdgpu_device_initialize()
* \param number_of_resources - \c [in] Number of BOs in the list
* \param resources - \c [in] List of BO handles
* \param resource_prios - \c [in] Optional priority for each handle
@@ -912,21 +842,6 @@
int amdgpu_cs_ctx_free(amdgpu_context_handle context);
/**
- * Override the submission priority for the given context using a master fd.
- *
- * \param dev - \c [in] device handle
- * \param context - \c [in] context handle for context id
- * \param master_fd - \c [in] The master fd to authorize the override.
- * \param priority - \c [in] The priority to assign to the context.
- *
- * \return 0 on success or a a negative Posix error code on failure.
- */
-int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
- amdgpu_context_handle context,
- int master_fd,
- unsigned priority);
-
-/**
* Query reset state for the specific GPU Context
*
* \param context - \c [in] GPU Context handle
@@ -1278,7 +1193,7 @@
* \notes \n
* It is client responsibility to correctly handle VA assignments and usage.
* Neither kernel driver nor libdrm_amdpgu are able to prevent and
- * detect wrong va assignment.
+ * detect wrong va assignemnt.
*
* It is client responsibility to correctly handle multi-GPU cases and to pass
* the corresponding arrays of all devices handles where corresponding VA will
@@ -1517,23 +1432,6 @@
const uint32_t *syncobjs, uint32_t syncobj_count);
/**
- * Signal kernel timeline sync objects.
- *
- * \param dev - \c [in] device handle
- * \param syncobjs - \c [in] array of sync object handles
- * \param points - \c [in] array of timeline points
- * \param syncobj_count - \c [in] number of handles in syncobjs
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
-*/
-int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
- const uint32_t *syncobjs,
- uint64_t *points,
- uint32_t syncobj_count);
-
-/**
* Wait for one or all sync objects to signal.
*
* \param dev - \c [in] self-explanatory
@@ -1554,45 +1452,6 @@
uint32_t *first_signaled);
/**
- * Wait for one or all sync objects on their points to signal.
- *
- * \param dev - \c [in] self-explanatory
- * \param handles - \c [in] array of sync object handles
- * \param points - \c [in] array of sync points to wait
- * \param num_handles - \c [in] self-explanatory
- * \param timeout_nsec - \c [in] self-explanatory
- * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
- * \param first_signaled - \c [in] self-explanatory
- *
- * \return 0 on success\n
- * -ETIME - Timeout
- * <0 - Negative POSIX Error code
- *
- */
-int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
- uint32_t *handles, uint64_t *points,
- unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled);
-/**
- * Query sync objects payloads.
- *
- * \param dev - \c [in] self-explanatory
- * \param handles - \c [in] array of sync object handles
- * \param points - \c [out] array of sync points returned, which presents
- * syncobj payload.
- * \param num_handles - \c [in] self-explanatory
- *
- * \return 0 on success\n
- * -ETIME - Timeout
- * <0 - Negative POSIX Error code
- *
- */
-int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
- uint32_t *handles, uint64_t *points,
- unsigned num_handles);
-
-/**
* Export kernel sync object to shareable fd.
*
* \param dev - \c [in] device handle
@@ -1650,62 +1509,6 @@
int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
uint32_t syncobj,
int sync_file_fd);
-/**
- * Export kernel timeline sync object to a sync_file.
- *
- * \param dev - \c [in] device handle
- * \param syncobj - \c [in] sync object handle
- * \param point - \c [in] timeline point
- * \param flags - \c [in] flags
- * \param sync_file_fd - \c [out] sync_file file descriptor.
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- */
-int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
- uint32_t syncobj,
- uint64_t point,
- uint32_t flags,
- int *sync_file_fd);
-
-/**
- * Import kernel timeline sync object from a sync_file.
- *
- * \param dev - \c [in] device handle
- * \param syncobj - \c [in] sync object handle
- * \param point - \c [in] timeline point
- * \param sync_file_fd - \c [in] sync_file file descriptor.
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- */
-int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
- uint32_t syncobj,
- uint64_t point,
- int sync_file_fd);
-
-/**
- * transfer between syncbojs.
- *
- * \param dev - \c [in] device handle
- * \param dst_handle - \c [in] sync object handle
- * \param dst_point - \c [in] timeline point, 0 presents dst is binary
- * \param src_handle - \c [in] sync object handle
- * \param src_point - \c [in] timeline point, 0 presents src is binary
- * \param flags - \c [in] flags
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- */
-int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev,
- uint32_t dst_handle,
- uint64_t dst_point,
- uint32_t src_handle,
- uint64_t src_point,
- uint32_t flags);
/**
* Export an amdgpu fence as a handle (syncobj or fd).
@@ -1746,28 +1549,6 @@
struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no);
-/**
- * Submit raw command submission to the kernel with a raw BO list handle.
- *
- * \param dev - \c [in] device handle
- * \param context - \c [in] context handle for context id
- * \param bo_list_handle - \c [in] raw bo list handle (0 for none)
- * \param num_chunks - \c [in] number of CS chunks to submit
- * \param chunks - \c [in] array of CS chunks
- * \param seq_no - \c [out] output sequence number for submission.
- *
- * \return 0 on success\n
- * <0 - Negative POSIX Error code
- *
- * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw()
- */
-int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
- amdgpu_context_handle context,
- uint32_t bo_list_handle,
- int num_chunks,
- struct drm_amdgpu_cs_chunk *chunks,
- uint64_t *seq_no);
-
void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
struct drm_amdgpu_cs_chunk_dep *dep);
void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index 5bdb8fe..9e37b14 100644
--- a/amdgpu/amdgpu_bo.c
+++ b/amdgpu/amdgpu_bo.c
@@ -37,79 +37,65 @@
#include "xf86drm.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
+#include "util_hash_table.h"
#include "util_math.h"
-static int amdgpu_close_kms_handle(int fd, uint32_t handle)
+static void amdgpu_close_kms_handle(amdgpu_device_handle dev,
+ uint32_t handle)
{
struct drm_gem_close args = {};
args.handle = handle;
- return drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &args);
+ drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &args);
}
-static int amdgpu_bo_create(amdgpu_device_handle dev,
- uint64_t size,
- uint32_t handle,
- amdgpu_bo_handle *buf_handle)
+int amdgpu_bo_alloc(amdgpu_device_handle dev,
+ struct amdgpu_bo_alloc_request *alloc_buffer,
+ amdgpu_bo_handle *buf_handle)
{
struct amdgpu_bo *bo;
- int r;
+ union drm_amdgpu_gem_create args;
+ unsigned heap = alloc_buffer->preferred_heap;
+ int r = 0;
+
+ /* It's an error if the heap is not specified */
+ if (!(heap & (AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM)))
+ return -EINVAL;
bo = calloc(1, sizeof(struct amdgpu_bo));
if (!bo)
return -ENOMEM;
- r = handle_table_insert(&dev->bo_handles, handle, bo);
- if (r) {
- free(bo);
- return r;
- }
-
atomic_set(&bo->refcount, 1);
bo->dev = dev;
- bo->alloc_size = size;
- bo->handle = handle;
- pthread_mutex_init(&bo->cpu_access_mutex, NULL);
-
- *buf_handle = bo;
- return 0;
-}
-
-drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev,
- struct amdgpu_bo_alloc_request *alloc_buffer,
- amdgpu_bo_handle *buf_handle)
-{
- union drm_amdgpu_gem_create args;
- int r;
+ bo->alloc_size = alloc_buffer->alloc_size;
memset(&args, 0, sizeof(args));
args.in.bo_size = alloc_buffer->alloc_size;
args.in.alignment = alloc_buffer->phys_alignment;
/* Set the placement. */
- args.in.domains = alloc_buffer->preferred_heap;
+ args.in.domains = heap;
args.in.domain_flags = alloc_buffer->flags;
/* Allocate the buffer with the preferred heap. */
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_CREATE,
&args, sizeof(args));
- if (r)
- goto out;
-
- pthread_mutex_lock(&dev->bo_table_mutex);
- r = amdgpu_bo_create(dev, alloc_buffer->alloc_size, args.out.handle,
- buf_handle);
- pthread_mutex_unlock(&dev->bo_table_mutex);
if (r) {
- amdgpu_close_kms_handle(dev->fd, args.out.handle);
+ free(bo);
+ return r;
}
-out:
- return r;
+ bo->handle = args.out.handle;
+
+ pthread_mutex_init(&bo->cpu_access_mutex, NULL);
+
+ *buf_handle = bo;
+ return 0;
}
-drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
- struct amdgpu_bo_metadata *info)
+int amdgpu_bo_set_metadata(amdgpu_bo_handle bo,
+ struct amdgpu_bo_metadata *info)
{
struct drm_amdgpu_gem_metadata args = {};
@@ -131,8 +117,8 @@
&args, sizeof(args));
}
-drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo,
- struct amdgpu_bo_info *info)
+int amdgpu_bo_query_info(amdgpu_bo_handle bo,
+ struct amdgpu_bo_info *info)
{
struct drm_amdgpu_gem_metadata metadata = {};
struct drm_amdgpu_gem_create_in bo_info = {};
@@ -182,6 +168,14 @@
return 0;
}
+static void amdgpu_add_handle_to_table(amdgpu_bo_handle bo)
+{
+ pthread_mutex_lock(&bo->dev->bo_table_mutex);
+ util_hash_table_set(bo->dev->bo_handles,
+ (void*)(uintptr_t)bo->handle, bo);
+ pthread_mutex_unlock(&bo->dev->bo_table_mutex);
+}
+
static int amdgpu_bo_export_flink(amdgpu_bo_handle bo)
{
struct drm_gem_flink flink;
@@ -215,19 +209,24 @@
bo->flink_name = flink.name;
- if (bo->dev->flink_fd != bo->dev->fd)
- amdgpu_close_kms_handle(bo->dev->flink_fd, handle);
+ if (bo->dev->flink_fd != bo->dev->fd) {
+ struct drm_gem_close args = {};
+ args.handle = handle;
+ drmIoctl(bo->dev->flink_fd, DRM_IOCTL_GEM_CLOSE, &args);
+ }
pthread_mutex_lock(&bo->dev->bo_table_mutex);
- r = handle_table_insert(&bo->dev->bo_flink_names, bo->flink_name, bo);
+ util_hash_table_set(bo->dev->bo_flink_names,
+ (void*)(uintptr_t)bo->flink_name,
+ bo);
pthread_mutex_unlock(&bo->dev->bo_table_mutex);
- return r;
+ return 0;
}
-drm_public int amdgpu_bo_export(amdgpu_bo_handle bo,
- enum amdgpu_bo_handle_type type,
- uint32_t *shared_handle)
+int amdgpu_bo_export(amdgpu_bo_handle bo,
+ enum amdgpu_bo_handle_type type,
+ uint32_t *shared_handle)
{
int r;
@@ -241,11 +240,12 @@
return 0;
case amdgpu_bo_handle_type_kms:
- case amdgpu_bo_handle_type_kms_noimport:
+ amdgpu_add_handle_to_table(bo);
*shared_handle = bo->handle;
return 0;
case amdgpu_bo_handle_type_dma_buf_fd:
+ amdgpu_add_handle_to_table(bo);
return drmPrimeHandleToFD(bo->dev->fd, bo->handle,
DRM_CLOEXEC | DRM_RDWR,
(int*)shared_handle);
@@ -253,16 +253,14 @@
return -EINVAL;
}
-drm_public int amdgpu_bo_import(amdgpu_device_handle dev,
- enum amdgpu_bo_handle_type type,
- uint32_t shared_handle,
+int amdgpu_bo_import(amdgpu_device_handle dev,
+ enum amdgpu_bo_handle_type type,
+ uint32_t shared_handle,
struct amdgpu_bo_import_result *output)
{
struct drm_gem_open open_arg = {};
struct amdgpu_bo *bo = NULL;
- uint32_t handle = 0, flink_name = 0;
- uint64_t alloc_size = 0;
- int r = 0;
+ int r;
int dma_fd;
uint64_t dma_buf_size = 0;
@@ -272,18 +270,22 @@
/* Convert a DMA buf handle to a KMS handle now. */
if (type == amdgpu_bo_handle_type_dma_buf_fd) {
+ uint32_t handle;
off_t size;
/* Get a KMS handle. */
r = drmPrimeFDToHandle(dev->fd, shared_handle, &handle);
- if (r)
- goto unlock;
+ if (r) {
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return r;
+ }
/* Query the buffer size. */
size = lseek(shared_handle, 0, SEEK_END);
if (size == (off_t)-1) {
- r = -errno;
- goto free_bo_handle;
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ amdgpu_close_kms_handle(dev, handle);
+ return -errno;
}
lseek(shared_handle, 0, SEEK_SET);
@@ -294,22 +296,23 @@
/* If we have already created a buffer with this handle, find it. */
switch (type) {
case amdgpu_bo_handle_type_gem_flink_name:
- bo = handle_table_lookup(&dev->bo_flink_names, shared_handle);
+ bo = util_hash_table_get(dev->bo_flink_names,
+ (void*)(uintptr_t)shared_handle);
break;
case amdgpu_bo_handle_type_dma_buf_fd:
- bo = handle_table_lookup(&dev->bo_handles, shared_handle);
+ bo = util_hash_table_get(dev->bo_handles,
+ (void*)(uintptr_t)shared_handle);
break;
case amdgpu_bo_handle_type_kms:
- case amdgpu_bo_handle_type_kms_noimport:
/* Importing a KMS handle in not allowed. */
- r = -EPERM;
- goto unlock;
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return -EPERM;
default:
- r = -EINVAL;
- goto unlock;
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return -EINVAL;
}
if (bo) {
@@ -322,77 +325,73 @@
return 0;
}
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo) {
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ if (type == amdgpu_bo_handle_type_dma_buf_fd) {
+ amdgpu_close_kms_handle(dev, shared_handle);
+ }
+ return -ENOMEM;
+ }
+
/* Open the handle. */
switch (type) {
case amdgpu_bo_handle_type_gem_flink_name:
open_arg.name = shared_handle;
r = drmIoctl(dev->flink_fd, DRM_IOCTL_GEM_OPEN, &open_arg);
- if (r)
- goto unlock;
-
- flink_name = shared_handle;
- handle = open_arg.handle;
- alloc_size = open_arg.size;
- if (dev->flink_fd != dev->fd) {
- r = drmPrimeHandleToFD(dev->flink_fd, handle,
- DRM_CLOEXEC, &dma_fd);
- if (r)
- goto free_bo_handle;
- r = drmPrimeFDToHandle(dev->fd, dma_fd, &handle);
- close(dma_fd);
- if (r)
- goto free_bo_handle;
- r = amdgpu_close_kms_handle(dev->flink_fd,
- open_arg.handle);
- if (r)
- goto free_bo_handle;
+ if (r) {
+ free(bo);
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return r;
}
- open_arg.handle = 0;
+
+ bo->handle = open_arg.handle;
+ if (dev->flink_fd != dev->fd) {
+ r = drmPrimeHandleToFD(dev->flink_fd, bo->handle, DRM_CLOEXEC, &dma_fd);
+ if (r) {
+ free(bo);
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return r;
+ }
+ r = drmPrimeFDToHandle(dev->fd, dma_fd, &bo->handle );
+
+ close(dma_fd);
+
+ if (r) {
+ free(bo);
+ pthread_mutex_unlock(&dev->bo_table_mutex);
+ return r;
+ }
+ }
+ bo->flink_name = shared_handle;
+ bo->alloc_size = open_arg.size;
+ util_hash_table_set(dev->bo_flink_names,
+ (void*)(uintptr_t)bo->flink_name, bo);
break;
case amdgpu_bo_handle_type_dma_buf_fd:
- handle = shared_handle;
- alloc_size = dma_buf_size;
+ bo->handle = shared_handle;
+ bo->alloc_size = dma_buf_size;
break;
case amdgpu_bo_handle_type_kms:
- case amdgpu_bo_handle_type_kms_noimport:
assert(0); /* unreachable */
}
/* Initialize it. */
- r = amdgpu_bo_create(dev, alloc_size, handle, &bo);
- if (r)
- goto free_bo_handle;
+ atomic_set(&bo->refcount, 1);
+ bo->dev = dev;
+ pthread_mutex_init(&bo->cpu_access_mutex, NULL);
- if (flink_name) {
- bo->flink_name = flink_name;
- r = handle_table_insert(&dev->bo_flink_names, flink_name,
- bo);
- if (r)
- goto free_bo_handle;
-
- }
+ util_hash_table_set(dev->bo_handles, (void*)(uintptr_t)bo->handle, bo);
+ pthread_mutex_unlock(&dev->bo_table_mutex);
output->buf_handle = bo;
output->alloc_size = bo->alloc_size;
- pthread_mutex_unlock(&dev->bo_table_mutex);
return 0;
-
-free_bo_handle:
- if (flink_name && open_arg.handle)
- amdgpu_close_kms_handle(dev->flink_fd, open_arg.handle);
-
- if (bo)
- amdgpu_bo_free(bo);
- else
- amdgpu_close_kms_handle(dev->fd, handle);
-unlock:
- pthread_mutex_unlock(&dev->bo_table_mutex);
- return r;
}
-drm_public int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
+int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
{
struct amdgpu_device *dev;
struct amdgpu_bo *bo = buf_handle;
@@ -403,11 +402,13 @@
if (update_references(&bo->refcount, NULL)) {
/* Remove the buffer from the hash tables. */
- handle_table_remove(&dev->bo_handles, bo->handle);
+ util_hash_table_remove(dev->bo_handles,
+ (void*)(uintptr_t)bo->handle);
- if (bo->flink_name)
- handle_table_remove(&dev->bo_flink_names,
- bo->flink_name);
+ if (bo->flink_name) {
+ util_hash_table_remove(dev->bo_flink_names,
+ (void*)(uintptr_t)bo->flink_name);
+ }
/* Release CPU access. */
if (bo->cpu_map_count > 0) {
@@ -415,22 +416,16 @@
amdgpu_bo_cpu_unmap(bo);
}
- amdgpu_close_kms_handle(dev->fd, bo->handle);
+ amdgpu_close_kms_handle(dev, bo->handle);
pthread_mutex_destroy(&bo->cpu_access_mutex);
free(bo);
}
pthread_mutex_unlock(&dev->bo_table_mutex);
-
return 0;
}
-drm_public void amdgpu_bo_inc_ref(amdgpu_bo_handle bo)
-{
- atomic_inc(&bo->refcount);
-}
-
-drm_public int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
+int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu)
{
union drm_amdgpu_gem_mmap args;
void *ptr;
@@ -478,7 +473,7 @@
return 0;
}
-drm_public int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
+int amdgpu_bo_cpu_unmap(amdgpu_bo_handle bo)
{
int r;
@@ -504,7 +499,7 @@
return r;
}
-drm_public int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
+int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments *info)
{
info->size_local = dev->dev_info.pte_fragment_size;
@@ -512,8 +507,8 @@
return 0;
}
-drm_public int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
- uint64_t timeout_ns,
+int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo,
+ uint64_t timeout_ns,
bool *busy)
{
union drm_amdgpu_gem_wait_idle args;
@@ -535,54 +530,13 @@
}
}
-drm_public int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- amdgpu_bo_handle *buf_handle,
- uint64_t *offset_in_bo)
-{
- struct amdgpu_bo *bo;
- uint32_t i;
- int r = 0;
-
- if (cpu == NULL || size == 0)
- return -EINVAL;
-
- /*
- * Workaround for a buggy application which tries to import previously
- * exposed CPU pointers. If we find a real world use case we should
- * improve that by asking the kernel for the right handle.
- */
- pthread_mutex_lock(&dev->bo_table_mutex);
- for (i = 0; i < dev->bo_handles.max_key; i++) {
- bo = handle_table_lookup(&dev->bo_handles, i);
- if (!bo || !bo->cpu_ptr || size > bo->alloc_size)
- continue;
- if (cpu >= bo->cpu_ptr &&
- cpu < (void*)((uintptr_t)bo->cpu_ptr + bo->alloc_size))
- break;
- }
-
- if (i < dev->bo_handles.max_key) {
- atomic_inc(&bo->refcount);
- *buf_handle = bo;
- *offset_in_bo = (uintptr_t)cpu - (uintptr_t)bo->cpu_ptr;
- } else {
- *buf_handle = NULL;
- *offset_in_bo = 0;
- r = -ENXIO;
- }
- pthread_mutex_unlock(&dev->bo_table_mutex);
-
- return r;
-}
-
-drm_public int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
- void *cpu,
- uint64_t size,
- amdgpu_bo_handle *buf_handle)
+int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
+ void *cpu,
+ uint64_t size,
+ amdgpu_bo_handle *buf_handle)
{
int r;
+ struct amdgpu_bo *bo;
struct drm_amdgpu_gem_userptr args;
args.addr = (uintptr_t)cpu;
@@ -592,58 +546,27 @@
r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_USERPTR,
&args, sizeof(args));
if (r)
- goto out;
+ return r;
- pthread_mutex_lock(&dev->bo_table_mutex);
- r = amdgpu_bo_create(dev, size, args.handle, buf_handle);
- pthread_mutex_unlock(&dev->bo_table_mutex);
- if (r) {
- amdgpu_close_kms_handle(dev->fd, args.handle);
- }
+ bo = calloc(1, sizeof(struct amdgpu_bo));
+ if (!bo)
+ return -ENOMEM;
-out:
+ atomic_set(&bo->refcount, 1);
+ bo->dev = dev;
+ bo->alloc_size = size;
+ bo->handle = args.handle;
+
+ *buf_handle = bo;
+
return r;
}
-drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev,
- uint32_t number_of_buffers,
- struct drm_amdgpu_bo_list_entry *buffers,
- uint32_t *result)
-{
- union drm_amdgpu_bo_list args;
- int r;
-
- memset(&args, 0, sizeof(args));
- args.in.operation = AMDGPU_BO_LIST_OP_CREATE;
- args.in.bo_number = number_of_buffers;
- args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry);
- args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers;
-
- r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
- &args, sizeof(args));
- if (!r)
- *result = args.out.list_handle;
- return r;
-}
-
-drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev,
- uint32_t bo_list)
-{
- union drm_amdgpu_bo_list args;
-
- memset(&args, 0, sizeof(args));
- args.in.operation = AMDGPU_BO_LIST_OP_DESTROY;
- args.in.list_handle = bo_list;
-
- return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST,
- &args, sizeof(args));
-}
-
-drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev,
- uint32_t number_of_resources,
- amdgpu_bo_handle *resources,
- uint8_t *resource_prios,
- amdgpu_bo_list_handle *result)
+int amdgpu_bo_list_create(amdgpu_device_handle dev,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios,
+ amdgpu_bo_list_handle *result)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
@@ -694,7 +617,7 @@
return 0;
}
-drm_public int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
+int amdgpu_bo_list_destroy(amdgpu_bo_list_handle list)
{
union drm_amdgpu_bo_list args;
int r;
@@ -712,10 +635,10 @@
return r;
}
-drm_public int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
- uint32_t number_of_resources,
- amdgpu_bo_handle *resources,
- uint8_t *resource_prios)
+int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
+ uint32_t number_of_resources,
+ amdgpu_bo_handle *resources,
+ uint8_t *resource_prios)
{
struct drm_amdgpu_bo_list_entry *list;
union drm_amdgpu_bo_list args;
@@ -753,12 +676,12 @@
return r;
}
-drm_public int amdgpu_bo_va_op(amdgpu_bo_handle bo,
- uint64_t offset,
- uint64_t size,
- uint64_t addr,
- uint64_t flags,
- uint32_t ops)
+int amdgpu_bo_va_op(amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops)
{
amdgpu_device_handle dev = bo->dev;
@@ -770,13 +693,13 @@
AMDGPU_VM_PAGE_EXECUTABLE, ops);
}
-drm_public int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
- amdgpu_bo_handle bo,
- uint64_t offset,
- uint64_t size,
- uint64_t addr,
- uint64_t flags,
- uint32_t ops)
+int amdgpu_bo_va_op_raw(amdgpu_device_handle dev,
+ amdgpu_bo_handle bo,
+ uint64_t offset,
+ uint64_t size,
+ uint64_t addr,
+ uint64_t flags,
+ uint32_t ops)
{
struct drm_amdgpu_gem_va va;
int r;
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 20d5aef..f986908 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -48,9 +48,8 @@
*
* \return 0 on success otherwise POSIX Error code
*/
-drm_public int amdgpu_cs_ctx_create2(amdgpu_device_handle dev,
- uint32_t priority,
- amdgpu_context_handle *context)
+int amdgpu_cs_ctx_create2(amdgpu_device_handle dev, uint32_t priority,
+ amdgpu_context_handle *context)
{
struct amdgpu_context *gpu_context;
union drm_amdgpu_ctx args;
@@ -94,8 +93,8 @@
return r;
}
-drm_public int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
- amdgpu_context_handle *context)
+int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
+ amdgpu_context_handle *context)
{
return amdgpu_cs_ctx_create2(dev, AMDGPU_CTX_PRIORITY_NORMAL, context);
}
@@ -108,7 +107,7 @@
*
* \return 0 on success otherwise POSIX Error code
*/
-drm_public int amdgpu_cs_ctx_free(amdgpu_context_handle context)
+int amdgpu_cs_ctx_free(amdgpu_context_handle context)
{
union drm_amdgpu_ctx args;
int i, j, k;
@@ -142,33 +141,8 @@
return r;
}
-drm_public int amdgpu_cs_ctx_override_priority(amdgpu_device_handle dev,
- amdgpu_context_handle context,
- int master_fd,
- unsigned priority)
-{
- union drm_amdgpu_sched args;
- int r;
-
- if (!dev || !context || master_fd < 0)
- return -EINVAL;
-
- memset(&args, 0, sizeof(args));
-
- args.in.op = AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE;
- args.in.fd = dev->fd;
- args.in.priority = priority;
- args.in.ctx_id = context->id;
-
- r = drmCommandWrite(master_fd, DRM_AMDGPU_SCHED, &args, sizeof(args));
- if (r)
- return r;
-
- return 0;
-}
-
-drm_public int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
- uint32_t *state, uint32_t *hangs)
+int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
+ uint32_t *state, uint32_t *hangs)
{
union drm_amdgpu_ctx args;
int r;
@@ -349,10 +323,10 @@
return r;
}
-drm_public int amdgpu_cs_submit(amdgpu_context_handle context,
- uint64_t flags,
- struct amdgpu_cs_request *ibs_request,
- uint32_t number_of_requests)
+int amdgpu_cs_submit(amdgpu_context_handle context,
+ uint64_t flags,
+ struct amdgpu_cs_request *ibs_request,
+ uint32_t number_of_requests)
{
uint32_t i;
int r;
@@ -433,10 +407,10 @@
return 0;
}
-drm_public int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
- uint64_t timeout_ns,
- uint64_t flags,
- uint32_t *expired)
+int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
+ uint64_t timeout_ns,
+ uint64_t flags,
+ uint32_t *expired)
{
bool busy = true;
int r;
@@ -504,12 +478,12 @@
return 0;
}
-drm_public int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
- uint32_t fence_count,
- bool wait_all,
- uint64_t timeout_ns,
- uint32_t *status,
- uint32_t *first)
+int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
+ uint32_t fence_count,
+ bool wait_all,
+ uint64_t timeout_ns,
+ uint32_t *status,
+ uint32_t *first)
{
uint32_t i;
@@ -532,7 +506,7 @@
timeout_ns, status, first);
}
-drm_public int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
+int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
{
struct amdgpu_semaphore *gpu_semaphore;
@@ -549,8 +523,8 @@
return 0;
}
-drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
- uint32_t ip_type,
+int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
+ uint32_t ip_type,
uint32_t ip_instance,
uint32_t ring,
amdgpu_semaphore_handle sem)
@@ -575,8 +549,8 @@
return 0;
}
-drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
- uint32_t ip_type,
+int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
+ uint32_t ip_type,
uint32_t ip_instance,
uint32_t ring,
amdgpu_semaphore_handle sem)
@@ -621,14 +595,14 @@
return 0;
}
-drm_public int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
+int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
{
return amdgpu_cs_unreference_sem(sem);
}
-drm_public int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
- uint32_t flags,
- uint32_t *handle)
+int amdgpu_cs_create_syncobj2(amdgpu_device_handle dev,
+ uint32_t flags,
+ uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@@ -636,8 +610,8 @@
return drmSyncobjCreate(dev->fd, flags, handle);
}
-drm_public int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
- uint32_t *handle)
+int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
+ uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@@ -645,8 +619,8 @@
return drmSyncobjCreate(dev->fd, 0, handle);
}
-drm_public int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
- uint32_t handle)
+int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
+ uint32_t handle)
{
if (NULL == dev)
return -EINVAL;
@@ -654,9 +628,8 @@
return drmSyncobjDestroy(dev->fd, handle);
}
-drm_public int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
- const uint32_t *syncobjs,
- uint32_t syncobj_count)
+int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
+ const uint32_t *syncobjs, uint32_t syncobj_count)
{
if (NULL == dev)
return -EINVAL;
@@ -664,9 +637,8 @@
return drmSyncobjReset(dev->fd, syncobjs, syncobj_count);
}
-drm_public int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
- const uint32_t *syncobjs,
- uint32_t syncobj_count)
+int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
+ const uint32_t *syncobjs, uint32_t syncobj_count)
{
if (NULL == dev)
return -EINVAL;
@@ -674,22 +646,10 @@
return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count);
}
-drm_public int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
- const uint32_t *syncobjs,
- uint64_t *points,
- uint32_t syncobj_count)
-{
- if (NULL == dev)
- return -EINVAL;
-
- return drmSyncobjTimelineSignal(dev->fd, syncobjs,
- points, syncobj_count);
-}
-
-drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
- uint32_t *handles, unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled)
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
{
if (NULL == dev)
return -EINVAL;
@@ -698,32 +658,9 @@
flags, first_signaled);
}
-drm_public int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
- uint32_t *handles, uint64_t *points,
- unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled)
-{
- if (NULL == dev)
- return -EINVAL;
-
- return drmSyncobjTimelineWait(dev->fd, handles, points, num_handles,
- timeout_nsec, flags, first_signaled);
-}
-
-drm_public int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
- uint32_t *handles, uint64_t *points,
- unsigned num_handles)
-{
- if (NULL == dev)
- return -EINVAL;
-
- return drmSyncobjQuery(dev->fd, handles, points, num_handles);
-}
-
-drm_public int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
- uint32_t handle,
- int *shared_fd)
+int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
+ uint32_t handle,
+ int *shared_fd)
{
if (NULL == dev)
return -EINVAL;
@@ -731,9 +668,9 @@
return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
}
-drm_public int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
- int shared_fd,
- uint32_t *handle)
+int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
+ int shared_fd,
+ uint32_t *handle)
{
if (NULL == dev)
return -EINVAL;
@@ -741,9 +678,9 @@
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
-drm_public int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
- uint32_t syncobj,
- int *sync_file_fd)
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd)
{
if (NULL == dev)
return -EINVAL;
@@ -751,9 +688,9 @@
return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
}
-drm_public int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
- uint32_t syncobj,
- int sync_file_fd)
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd)
{
if (NULL == dev)
return -EINVAL;
@@ -761,84 +698,12 @@
return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
}
-drm_public int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
- uint32_t syncobj,
- uint64_t point,
- uint32_t flags,
- int *sync_file_fd)
-{
- uint32_t binary_handle;
- int ret;
-
- if (NULL == dev)
- return -EINVAL;
-
- if (!point)
- return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
-
- ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
- if (ret)
- return ret;
-
- ret = drmSyncobjTransfer(dev->fd, binary_handle, 0,
- syncobj, point, flags);
- if (ret)
- goto out;
- ret = drmSyncobjExportSyncFile(dev->fd, binary_handle, sync_file_fd);
-out:
- drmSyncobjDestroy(dev->fd, binary_handle);
- return ret;
-}
-
-drm_public int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
- uint32_t syncobj,
- uint64_t point,
- int sync_file_fd)
-{
- uint32_t binary_handle;
- int ret;
-
- if (NULL == dev)
- return -EINVAL;
-
- if (!point)
- return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
-
- ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
- if (ret)
- return ret;
- ret = drmSyncobjImportSyncFile(dev->fd, binary_handle, sync_file_fd);
- if (ret)
- goto out;
- ret = drmSyncobjTransfer(dev->fd, syncobj, point,
- binary_handle, 0, 0);
-out:
- drmSyncobjDestroy(dev->fd, binary_handle);
- return ret;
-}
-
-drm_public int amdgpu_cs_syncobj_transfer(amdgpu_device_handle dev,
- uint32_t dst_handle,
- uint64_t dst_point,
- uint32_t src_handle,
- uint64_t src_point,
- uint32_t flags)
-{
- if (NULL == dev)
- return -EINVAL;
-
- return drmSyncobjTransfer(dev->fd,
- dst_handle, dst_point,
- src_handle, src_point,
- flags);
-}
-
-drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
- amdgpu_context_handle context,
- amdgpu_bo_list_handle bo_list_handle,
- int num_chunks,
- struct drm_amdgpu_cs_chunk *chunks,
- uint64_t *seq_no)
+int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
+ amdgpu_context_handle context,
+ amdgpu_bo_list_handle bo_list_handle,
+ int num_chunks,
+ struct drm_amdgpu_cs_chunk *chunks,
+ uint64_t *seq_no)
{
union drm_amdgpu_cs cs;
uint64_t *chunk_array;
@@ -864,41 +729,15 @@
return 0;
}
-drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev,
- amdgpu_context_handle context,
- uint32_t bo_list_handle,
- int num_chunks,
- struct drm_amdgpu_cs_chunk *chunks,
- uint64_t *seq_no)
-{
- union drm_amdgpu_cs cs;
- uint64_t *chunk_array;
- int i, r;
-
- memset(&cs, 0, sizeof(cs));
- chunk_array = alloca(sizeof(uint64_t) * num_chunks);
- for (i = 0; i < num_chunks; i++)
- chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
- cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
- cs.in.ctx_id = context->id;
- cs.in.bo_list_handle = bo_list_handle;
- cs.in.num_chunks = num_chunks;
- r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
- &cs, sizeof(cs));
- if (!r && seq_no)
- *seq_no = cs.out.handle;
- return r;
-}
-
-drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
+void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
struct drm_amdgpu_cs_chunk_data *data)
{
data->fence_data.handle = fence_info->handle->handle;
data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
}
-drm_public void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
- struct drm_amdgpu_cs_chunk_dep *dep)
+void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
+ struct drm_amdgpu_cs_chunk_dep *dep)
{
dep->ip_type = fence->ip_type;
dep->ip_instance = fence->ip_instance;
@@ -907,10 +746,10 @@
dep->handle = fence->fence;
}
-drm_public int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
- struct amdgpu_cs_fence *fence,
- uint32_t what,
- uint32_t *out_handle)
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
{
union drm_amdgpu_fence_to_handle fth;
int r;
diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index 76b4e5e..d81efcf 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -34,20 +34,51 @@
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
-#include <fcntl.h>
#include "xf86drm.h"
#include "amdgpu_drm.h"
#include "amdgpu_internal.h"
+#include "util_hash_table.h"
#include "util_math.h"
#define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
+#define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
-static pthread_mutex_t dev_mutex = PTHREAD_MUTEX_INITIALIZER;
-static amdgpu_device_handle dev_list;
+static pthread_mutex_t fd_mutex = PTHREAD_MUTEX_INITIALIZER;
+static struct util_hash_table *fd_tab;
-static int fd_compare(int fd1, int fd2)
+static unsigned handle_hash(void *key)
{
+ return PTR_TO_UINT(key);
+}
+
+static int handle_compare(void *key1, void *key2)
+{
+ return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
+}
+
+static unsigned fd_hash(void *key)
+{
+ int fd = PTR_TO_UINT(key);
+ char *name = drmGetPrimaryDeviceNameFromFd(fd);
+ unsigned result = 0;
+ char *c;
+
+ if (name == NULL)
+ return 0;
+
+ for (c = name; *c; ++c)
+ result += *c;
+
+ free(name);
+
+ return result;
+}
+
+static int fd_compare(void *key1, void *key2)
+{
+ int fd1 = PTR_TO_UINT(key1);
+ int fd2 = PTR_TO_UINT(key2);
char *name1 = drmGetPrimaryDeviceNameFromFd(fd1);
char *name2 = drmGetPrimaryDeviceNameFromFd(fd2);
int result;
@@ -95,25 +126,15 @@
static void amdgpu_device_free_internal(amdgpu_device_handle dev)
{
- amdgpu_device_handle *node = &dev_list;
-
- pthread_mutex_lock(&dev_mutex);
- while (*node != dev && (*node)->next)
- node = &(*node)->next;
- *node = (*node)->next;
- pthread_mutex_unlock(&dev_mutex);
-
+ amdgpu_vamgr_deinit(&dev->vamgr_32);
+ amdgpu_vamgr_deinit(&dev->vamgr);
+ util_hash_table_destroy(dev->bo_flink_names);
+ util_hash_table_destroy(dev->bo_handles);
+ pthread_mutex_destroy(&dev->bo_table_mutex);
+ util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
close(dev->fd);
if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
close(dev->flink_fd);
-
- amdgpu_vamgr_deinit(&dev->vamgr_32);
- amdgpu_vamgr_deinit(&dev->vamgr);
- amdgpu_vamgr_deinit(&dev->vamgr_high_32);
- amdgpu_vamgr_deinit(&dev->vamgr_high);
- handle_table_fini(&dev->bo_handles);
- handle_table_fini(&dev->bo_flink_names);
- pthread_mutex_destroy(&dev->bo_table_mutex);
free(dev->marketing_name);
free(dev);
}
@@ -133,17 +154,17 @@
* // incremented. dst is freed if its reference counter is 0.
*/
static void amdgpu_device_reference(struct amdgpu_device **dst,
- struct amdgpu_device *src)
+ struct amdgpu_device *src)
{
if (update_references(&(*dst)->refcount, &src->refcount))
amdgpu_device_free_internal(*dst);
*dst = src;
}
-drm_public int amdgpu_device_initialize(int fd,
- uint32_t *major_version,
- uint32_t *minor_version,
- amdgpu_device_handle *device_handle)
+int amdgpu_device_initialize(int fd,
+ uint32_t *major_version,
+ uint32_t *minor_version,
+ amdgpu_device_handle *device_handle)
{
struct amdgpu_device *dev;
drmVersionPtr version;
@@ -155,41 +176,39 @@
*device_handle = NULL;
- pthread_mutex_lock(&dev_mutex);
+ pthread_mutex_lock(&fd_mutex);
+ if (!fd_tab)
+ fd_tab = util_hash_table_create(fd_hash, fd_compare);
r = amdgpu_get_auth(fd, &flag_auth);
if (r) {
fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n",
__func__, r);
- pthread_mutex_unlock(&dev_mutex);
+ pthread_mutex_unlock(&fd_mutex);
return r;
}
-
- for (dev = dev_list; dev; dev = dev->next)
- if (fd_compare(dev->fd, fd) == 0)
- break;
-
+ dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
if (dev) {
r = amdgpu_get_auth(dev->fd, &flag_authexist);
if (r) {
fprintf(stderr, "%s: amdgpu_get_auth (2) failed (%i)\n",
__func__, r);
- pthread_mutex_unlock(&dev_mutex);
+ pthread_mutex_unlock(&fd_mutex);
return r;
}
if ((flag_auth) && (!flag_authexist)) {
- dev->flink_fd = fcntl(fd, F_DUPFD_CLOEXEC, 0);
+ dev->flink_fd = dup(fd);
}
*major_version = dev->major_version;
*minor_version = dev->minor_version;
amdgpu_device_reference(device_handle, dev);
- pthread_mutex_unlock(&dev_mutex);
+ pthread_mutex_unlock(&fd_mutex);
return 0;
}
dev = calloc(1, sizeof(struct amdgpu_device));
if (!dev) {
fprintf(stderr, "%s: calloc failed\n", __func__);
- pthread_mutex_unlock(&dev_mutex);
+ pthread_mutex_unlock(&fd_mutex);
return -ENOMEM;
}
@@ -211,12 +230,15 @@
goto cleanup;
}
- dev->fd = fcntl(fd, F_DUPFD_CLOEXEC, 0);
+ dev->fd = dup(fd);
dev->flink_fd = dev->fd;
dev->major_version = version->version_major;
dev->minor_version = version->version_minor;
drmFreeVersion(version);
+ dev->bo_flink_names = util_hash_table_create(handle_hash,
+ handle_compare);
+ dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
pthread_mutex_init(&dev->bo_table_mutex, NULL);
/* Check if acceleration is working. */
@@ -265,9 +287,8 @@
*major_version = dev->major_version;
*minor_version = dev->minor_version;
*device_handle = dev;
- dev->next = dev_list;
- dev_list = dev;
- pthread_mutex_unlock(&dev_mutex);
+ util_hash_table_set(fd_tab, UINT_TO_PTR(dev->fd), dev);
+ pthread_mutex_unlock(&fd_mutex);
return 0;
@@ -275,24 +296,23 @@
if (dev->fd >= 0)
close(dev->fd);
free(dev);
- pthread_mutex_unlock(&dev_mutex);
+ pthread_mutex_unlock(&fd_mutex);
return r;
}
-drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev)
+int amdgpu_device_deinitialize(amdgpu_device_handle dev)
{
amdgpu_device_reference(&dev, NULL);
return 0;
}
-drm_public const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
+const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
return dev->marketing_name;
}
-drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev,
- enum amdgpu_sw_info info,
- void *value)
+int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
+ void *value)
{
uint32_t *val32 = (uint32_t*)value;
diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 777087f..b68e1c4 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -30,8 +30,8 @@
#include "amdgpu_internal.h"
#include "xf86drm.h"
-drm_public int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
- unsigned size, void *value)
+int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
+ unsigned size, void *value)
{
struct drm_amdgpu_info request;
@@ -44,8 +44,8 @@
sizeof(struct drm_amdgpu_info));
}
-drm_public int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
- int32_t *result)
+int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
+ int32_t *result)
{
struct drm_amdgpu_info request;
@@ -59,9 +59,9 @@
sizeof(struct drm_amdgpu_info));
}
-drm_public int amdgpu_read_mm_registers(amdgpu_device_handle dev,
- unsigned dword_offset, unsigned count, uint32_t instance,
- uint32_t flags, uint32_t *values)
+int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
+ unsigned count, uint32_t instance, uint32_t flags,
+ uint32_t *values)
{
struct drm_amdgpu_info request;
@@ -78,9 +78,8 @@
sizeof(struct drm_amdgpu_info));
}
-drm_public int amdgpu_query_hw_ip_count(amdgpu_device_handle dev,
- unsigned type,
- uint32_t *count)
+int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
+ uint32_t *count)
{
struct drm_amdgpu_info request;
@@ -94,9 +93,9 @@
sizeof(struct drm_amdgpu_info));
}
-drm_public int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
- unsigned ip_instance,
- struct drm_amdgpu_info_hw_ip *info)
+int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
+ unsigned ip_instance,
+ struct drm_amdgpu_info_hw_ip *info)
{
struct drm_amdgpu_info request;
@@ -111,9 +110,9 @@
sizeof(struct drm_amdgpu_info));
}
-drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev,
- unsigned fw_type, unsigned ip_instance, unsigned index,
- uint32_t *version, uint32_t *feature)
+int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
+ unsigned ip_instance, unsigned index,
+ uint32_t *version, uint32_t *feature)
{
struct drm_amdgpu_info request;
struct drm_amdgpu_info_firmware firmware = {};
@@ -228,8 +227,8 @@
return 0;
}
-drm_public int amdgpu_query_gpu_info(amdgpu_device_handle dev,
- struct amdgpu_gpu_info *info)
+int amdgpu_query_gpu_info(amdgpu_device_handle dev,
+ struct amdgpu_gpu_info *info)
{
if (!dev || !info)
return -EINVAL;
@@ -240,10 +239,10 @@
return 0;
}
-drm_public int amdgpu_query_heap_info(amdgpu_device_handle dev,
- uint32_t heap,
- uint32_t flags,
- struct amdgpu_heap_info *info)
+int amdgpu_query_heap_info(amdgpu_device_handle dev,
+ uint32_t heap,
+ uint32_t flags,
+ struct amdgpu_heap_info *info)
{
struct drm_amdgpu_info_vram_gtt vram_gtt_info = {};
int r;
@@ -292,8 +291,8 @@
return 0;
}
-drm_public int amdgpu_query_gds_info(amdgpu_device_handle dev,
- struct amdgpu_gds_resource_info *gds_info)
+int amdgpu_query_gds_info(amdgpu_device_handle dev,
+ struct amdgpu_gds_resource_info *gds_info)
{
struct drm_amdgpu_info_gds gds_config = {};
int r;
@@ -317,8 +316,8 @@
return 0;
}
-drm_public int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
- unsigned size, void *value)
+int amdgpu_query_sensor_info(amdgpu_device_handle dev, unsigned sensor_type,
+ unsigned size, void *value)
{
struct drm_amdgpu_info request;
diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h
index a340abb..99b8ce0 100644
--- a/amdgpu/amdgpu_internal.h
+++ b/amdgpu/amdgpu_internal.h
@@ -32,7 +32,6 @@
#include "xf86atomic.h"
#include "amdgpu.h"
#include "util_double_list.h"
-#include "handle_table.h"
#define AMDGPU_CS_MAX_RINGS 8
/* do not use below macro if b is not power of 2 aligned value */
@@ -66,7 +65,6 @@
struct amdgpu_device {
atomic_t refcount;
- struct amdgpu_device *next;
int fd;
int flink_fd;
unsigned major_version;
@@ -74,9 +72,9 @@
char *marketing_name;
/** List of buffer handles. Protected by bo_table_mutex. */
- struct handle_table bo_handles;
+ struct util_hash_table *bo_handles;
/** List of buffer GEM flink names. Protected by bo_table_mutex. */
- struct handle_table bo_flink_names;
+ struct util_hash_table *bo_flink_names;
/** This protects all hash tables. */
pthread_mutex_t bo_table_mutex;
struct drm_amdgpu_info_device dev_info;
diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c
index d25d421..1de9f95 100644
--- a/amdgpu/amdgpu_vamgr.c
+++ b/amdgpu/amdgpu_vamgr.c
@@ -29,9 +29,9 @@
#include "amdgpu_internal.h"
#include "util_math.h"
-drm_public int amdgpu_va_range_query(amdgpu_device_handle dev,
- enum amdgpu_gpu_va_range type,
- uint64_t *start, uint64_t *end)
+int amdgpu_va_range_query(amdgpu_device_handle dev,
+ enum amdgpu_gpu_va_range type,
+ uint64_t *start, uint64_t *end)
{
if (type != amdgpu_gpu_va_range_general)
return -EINVAL;
@@ -186,14 +186,14 @@
pthread_mutex_unlock(&mgr->bo_va_mutex);
}
-drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev,
- enum amdgpu_gpu_va_range va_range_type,
- uint64_t size,
- uint64_t va_base_alignment,
- uint64_t va_base_required,
- uint64_t *va_base_allocated,
- amdgpu_va_handle *va_range_handle,
- uint64_t flags)
+int amdgpu_va_range_alloc(amdgpu_device_handle dev,
+ enum amdgpu_gpu_va_range va_range_type,
+ uint64_t size,
+ uint64_t va_base_alignment,
+ uint64_t va_base_required,
+ uint64_t *va_base_allocated,
+ amdgpu_va_handle *va_range_handle,
+ uint64_t flags)
{
struct amdgpu_bo_va_mgr *vamgr;
@@ -250,7 +250,7 @@
return 0;
}
-drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
+int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
{
if(!va_range_handle || !va_range_handle->address)
return 0;
diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c
index 7e6e28f..da9d07f 100644
--- a/amdgpu/amdgpu_vm.c
+++ b/amdgpu/amdgpu_vm.c
@@ -26,7 +26,7 @@
#include "xf86drm.h"
#include "amdgpu_internal.h"
-drm_public int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags)
+int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags)
{
union drm_amdgpu_vm vm;
@@ -37,8 +37,7 @@
&vm, sizeof(vm));
}
-drm_public int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev,
- uint32_t flags)
+int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags)
{
union drm_amdgpu_vm vm;
diff --git a/amdgpu/handle_table.c b/amdgpu/handle_table.c
deleted file mode 100644
index 4fdd29d..0000000
--- a/amdgpu/handle_table.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include <unistd.h>
-#include "handle_table.h"
-#include "util_math.h"
-
-drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
- void *value)
-{
- if (key >= table->max_key) {
- uint32_t alignment = sysconf(_SC_PAGESIZE) / sizeof(void*);
- uint32_t max_key = ALIGN(key + 1, alignment);
- void **values;
-
- values = realloc(table->values, max_key * sizeof(void *));
- if (!values)
- return -ENOMEM;
-
- memset(values + table->max_key, 0, (max_key - table->max_key) *
- sizeof(void *));
-
- table->max_key = max_key;
- table->values = values;
- }
- table->values[key] = value;
- return 0;
-}
-
-drm_private void handle_table_remove(struct handle_table *table, uint32_t key)
-{
- if (key < table->max_key)
- table->values[key] = NULL;
-}
-
-drm_private void *handle_table_lookup(struct handle_table *table, uint32_t key)
-{
- if (key < table->max_key)
- return table->values[key];
- else
- return NULL;
-}
-
-drm_private void handle_table_fini(struct handle_table *table)
-{
- free(table->values);
- table->max_key = 0;
- table->values = NULL;
-}
diff --git a/amdgpu/handle_table.h b/amdgpu/handle_table.h
deleted file mode 100644
index 461193f..0000000
--- a/amdgpu/handle_table.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _HANDLE_TABLE_H_
-#define _HANDLE_TABLE_H_
-
-#include <stdint.h>
-#include "libdrm_macros.h"
-
-struct handle_table {
- uint32_t max_key;
- void **values;
-};
-
-drm_private int handle_table_insert(struct handle_table *table, uint32_t key,
- void *value);
-drm_private void handle_table_remove(struct handle_table *table, uint32_t key);
-drm_private void *handle_table_lookup(struct handle_table *table, uint32_t key);
-drm_private void handle_table_fini(struct handle_table *table);
-
-#endif /* _HANDLE_TABLE_H_ */
diff --git a/amdgpu/meson.build b/amdgpu/meson.build
index 7c8ccc7..f39d7bf 100644
--- a/amdgpu/meson.build
+++ b/amdgpu/meson.build
@@ -26,12 +26,13 @@
[
files(
'amdgpu_asic_id.c', 'amdgpu_bo.c', 'amdgpu_cs.c', 'amdgpu_device.c',
- 'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'handle_table.c',
+ 'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'util_hash.c',
+ 'util_hash_table.c',
),
config_file,
],
c_args : [
- libdrm_c_args,
+ warn_c_args,
'-DAMDGPU_ASIC_ID_TABLE="@0@"'.format(join_paths(datadir_amdgpu, 'amdgpu.ids')),
],
include_directories : [inc_root, inc_drm],
diff --git a/amdgpu/util_hash.c b/amdgpu/util_hash.c
new file mode 100644
index 0000000..7e59041
--- /dev/null
+++ b/amdgpu/util_hash.c
@@ -0,0 +1,383 @@
+/**************************************************************************
+ *
+ * Copyright 2007 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+ /*
+ * Authors:
+ * Zack Rusin <zackr@vmware.com>
+ */
+
+#include "util_hash.h"
+
+#include <stdlib.h>
+#include <assert.h>
+
+#define MAX(a, b) ((a > b) ? (a) : (b))
+
+static const int MinNumBits = 4;
+
+static const unsigned char prime_deltas[] = {
+ 0, 0, 1, 3, 1, 5, 3, 3, 1, 9, 7, 5, 3, 9, 25, 3,
+ 1, 21, 3, 21, 7, 15, 9, 5, 3, 29, 15, 0, 0, 0, 0, 0
+};
+
+static int primeForNumBits(int numBits)
+{
+ return (1 << numBits) + prime_deltas[numBits];
+}
+
+/* Returns the smallest integer n such that
+ primeForNumBits(n) >= hint.
+*/
+static int countBits(int hint)
+{
+ int numBits = 0;
+ int bits = hint;
+
+ while (bits > 1) {
+ bits >>= 1;
+ numBits++;
+ }
+
+ if (numBits >= (int)sizeof(prime_deltas)) {
+ numBits = sizeof(prime_deltas) - 1;
+ } else if (primeForNumBits(numBits) < hint) {
+ ++numBits;
+ }
+ return numBits;
+}
+
+struct util_node {
+ struct util_node *next;
+ unsigned key;
+ void *value;
+};
+
+struct util_hash_data {
+ struct util_node *fakeNext;
+ struct util_node **buckets;
+ int size;
+ int nodeSize;
+ short userNumBits;
+ short numBits;
+ int numBuckets;
+};
+
+struct util_hash {
+ union {
+ struct util_hash_data *d;
+ struct util_node *e;
+ } data;
+};
+
+static void *util_data_allocate_node(struct util_hash_data *hash)
+{
+ return malloc(hash->nodeSize);
+}
+
+static void util_free_node(struct util_node *node)
+{
+ free(node);
+}
+
+static struct util_node *
+util_hash_create_node(struct util_hash *hash,
+ unsigned akey, void *avalue,
+ struct util_node **anextNode)
+{
+ struct util_node *node = util_data_allocate_node(hash->data.d);
+
+ if (!node)
+ return NULL;
+
+ node->key = akey;
+ node->value = avalue;
+
+ node->next = (struct util_node*)(*anextNode);
+ *anextNode = node;
+ ++hash->data.d->size;
+ return node;
+}
+
+static void util_data_rehash(struct util_hash_data *hash, int hint)
+{
+ if (hint < 0) {
+ hint = countBits(-hint);
+ if (hint < MinNumBits)
+ hint = MinNumBits;
+ hash->userNumBits = (short)hint;
+ while (primeForNumBits(hint) < (hash->size >> 1))
+ ++hint;
+ } else if (hint < MinNumBits) {
+ hint = MinNumBits;
+ }
+
+ if (hash->numBits != hint) {
+ struct util_node *e = (struct util_node *)(hash);
+ struct util_node **oldBuckets = hash->buckets;
+ int oldNumBuckets = hash->numBuckets;
+ int i = 0;
+
+ hash->numBits = (short)hint;
+ hash->numBuckets = primeForNumBits(hint);
+ hash->buckets = malloc(sizeof(struct util_node*) * hash->numBuckets);
+ for (i = 0; i < hash->numBuckets; ++i)
+ hash->buckets[i] = e;
+
+ for (i = 0; i < oldNumBuckets; ++i) {
+ struct util_node *firstNode = oldBuckets[i];
+ while (firstNode != e) {
+ unsigned h = firstNode->key;
+ struct util_node *lastNode = firstNode;
+ struct util_node *afterLastNode;
+ struct util_node **beforeFirstNode;
+
+ while (lastNode->next != e && lastNode->next->key == h)
+ lastNode = lastNode->next;
+
+ afterLastNode = lastNode->next;
+ beforeFirstNode = &hash->buckets[h % hash->numBuckets];
+ while (*beforeFirstNode != e)
+ beforeFirstNode = &(*beforeFirstNode)->next;
+ lastNode->next = *beforeFirstNode;
+ *beforeFirstNode = firstNode;
+ firstNode = afterLastNode;
+ }
+ }
+ free(oldBuckets);
+ }
+}
+
+static void util_data_might_grow(struct util_hash_data *hash)
+{
+ if (hash->size >= hash->numBuckets)
+ util_data_rehash(hash, hash->numBits + 1);
+}
+
+static void util_data_has_shrunk(struct util_hash_data *hash)
+{
+ if (hash->size <= (hash->numBuckets >> 3) &&
+ hash->numBits > hash->userNumBits) {
+ int max = MAX(hash->numBits-2, hash->userNumBits);
+ util_data_rehash(hash, max);
+ }
+}
+
+static struct util_node *util_data_first_node(struct util_hash_data *hash)
+{
+ struct util_node *e = (struct util_node *)(hash);
+ struct util_node **bucket = hash->buckets;
+ int n = hash->numBuckets;
+ while (n--) {
+ if (*bucket != e)
+ return *bucket;
+ ++bucket;
+ }
+ return e;
+}
+
+static struct util_node **util_hash_find_node(struct util_hash *hash, unsigned akey)
+{
+ struct util_node **node;
+
+ if (hash->data.d->numBuckets) {
+ node = (struct util_node **)(&hash->data.d->buckets[akey % hash->data.d->numBuckets]);
+ assert(*node == hash->data.e || (*node)->next);
+ while (*node != hash->data.e && (*node)->key != akey)
+ node = &(*node)->next;
+ } else {
+ node = (struct util_node **)((const struct util_node * const *)(&hash->data.e));
+ }
+ return node;
+}
+
+drm_private struct util_hash_iter
+util_hash_insert(struct util_hash *hash, unsigned key, void *data)
+{
+ util_data_might_grow(hash->data.d);
+
+ {
+ struct util_node **nextNode = util_hash_find_node(hash, key);
+ struct util_node *node = util_hash_create_node(hash, key, data, nextNode);
+ if (!node) {
+ struct util_hash_iter null_iter = {hash, 0};
+ return null_iter;
+ }
+
+ {
+ struct util_hash_iter iter = {hash, node};
+ return iter;
+ }
+ }
+}
+
+drm_private struct util_hash *util_hash_create(void)
+{
+ struct util_hash *hash = malloc(sizeof(struct util_hash));
+ if (!hash)
+ return NULL;
+
+ hash->data.d = malloc(sizeof(struct util_hash_data));
+ if (!hash->data.d) {
+ free(hash);
+ return NULL;
+ }
+
+ hash->data.d->fakeNext = 0;
+ hash->data.d->buckets = 0;
+ hash->data.d->size = 0;
+ hash->data.d->nodeSize = sizeof(struct util_node);
+ hash->data.d->userNumBits = (short)MinNumBits;
+ hash->data.d->numBits = 0;
+ hash->data.d->numBuckets = 0;
+
+ return hash;
+}
+
+drm_private void util_hash_delete(struct util_hash *hash)
+{
+ struct util_node *e_for_x = (struct util_node *)(hash->data.d);
+ struct util_node **bucket = (struct util_node **)(hash->data.d->buckets);
+ int n = hash->data.d->numBuckets;
+ while (n--) {
+ struct util_node *cur = *bucket++;
+ while (cur != e_for_x) {
+ struct util_node *next = cur->next;
+ util_free_node(cur);
+ cur = next;
+ }
+ }
+ free(hash->data.d->buckets);
+ free(hash->data.d);
+ free(hash);
+}
+
+drm_private struct util_hash_iter
+util_hash_find(struct util_hash *hash, unsigned key)
+{
+ struct util_node **nextNode = util_hash_find_node(hash, key);
+ struct util_hash_iter iter = {hash, *nextNode};
+ return iter;
+}
+
+drm_private unsigned util_hash_iter_key(struct util_hash_iter iter)
+{
+ if (!iter.node || iter.hash->data.e == iter.node)
+ return 0;
+ return iter.node->key;
+}
+
+drm_private void *util_hash_iter_data(struct util_hash_iter iter)
+{
+ if (!iter.node || iter.hash->data.e == iter.node)
+ return 0;
+ return iter.node->value;
+}
+
+static struct util_node *util_hash_data_next(struct util_node *node)
+{
+ union {
+ struct util_node *next;
+ struct util_node *e;
+ struct util_hash_data *d;
+ } a;
+ int start;
+ struct util_node **bucket;
+ int n;
+
+ a.next = node->next;
+ if (!a.next) {
+ /* iterating beyond the last element */
+ return 0;
+ }
+ if (a.next->next)
+ return a.next;
+
+ start = (node->key % a.d->numBuckets) + 1;
+ bucket = a.d->buckets + start;
+ n = a.d->numBuckets - start;
+ while (n--) {
+ if (*bucket != a.e)
+ return *bucket;
+ ++bucket;
+ }
+ return a.e;
+}
+
+drm_private struct util_hash_iter
+util_hash_iter_next(struct util_hash_iter iter)
+{
+ struct util_hash_iter next = {iter.hash, util_hash_data_next(iter.node)};
+ return next;
+}
+
+drm_private int util_hash_iter_is_null(struct util_hash_iter iter)
+{
+ if (!iter.node || iter.node == iter.hash->data.e)
+ return 1;
+ return 0;
+}
+
+drm_private void *util_hash_take(struct util_hash *hash, unsigned akey)
+{
+ struct util_node **node = util_hash_find_node(hash, akey);
+ if (*node != hash->data.e) {
+ void *t = (*node)->value;
+ struct util_node *next = (*node)->next;
+ util_free_node(*node);
+ *node = next;
+ --hash->data.d->size;
+ util_data_has_shrunk(hash->data.d);
+ return t;
+ }
+ return 0;
+}
+
+drm_private struct util_hash_iter util_hash_first_node(struct util_hash *hash)
+{
+ struct util_hash_iter iter = {hash, util_data_first_node(hash->data.d)};
+ return iter;
+}
+
+drm_private struct util_hash_iter
+util_hash_erase(struct util_hash *hash, struct util_hash_iter iter)
+{
+ struct util_hash_iter ret = iter;
+ struct util_node *node = iter.node;
+ struct util_node **node_ptr;
+
+ if (node == hash->data.e)
+ return iter;
+
+ ret = util_hash_iter_next(ret);
+ node_ptr = (struct util_node**)(&hash->data.d->buckets[node->key % hash->data.d->numBuckets]);
+ while (*node_ptr != node)
+ node_ptr = &(*node_ptr)->next;
+ *node_ptr = node->next;
+ util_free_node(node);
+ --hash->data.d->size;
+ return ret;
+}
diff --git a/amdgpu/util_hash.h b/amdgpu/util_hash.h
new file mode 100644
index 0000000..6eed156
--- /dev/null
+++ b/amdgpu/util_hash.h
@@ -0,0 +1,103 @@
+/**************************************************************************
+ *
+ * Copyright 2007 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/**
+ * @file
+ * Hash implementation.
+ *
+ * This file provides a hash implementation that is capable of dealing
+ * with collisions. It stores colliding entries in linked list. All
+ * functions operating on the hash return an iterator. The iterator
+ * itself points to the collision list. If there wasn't any collision
+ * the list will have just one entry, otherwise client code should
+ * iterate over the entries to find the exact entry among ones that
+ * had the same key (e.g. memcmp could be used on the data to check
+ * that)
+ *
+ * @author Zack Rusin <zackr@vmware.com>
+ */
+
+#ifndef UTIL_HASH_H
+#define UTIL_HASH_H
+
+#include <stdbool.h>
+
+#include "libdrm_macros.h"
+
+struct util_hash;
+struct util_node;
+
+struct util_hash_iter {
+ struct util_hash *hash;
+ struct util_node *node;
+};
+
+
+drm_private struct util_hash *util_hash_create(void);
+drm_private void util_hash_delete(struct util_hash *hash);
+
+
+/**
+ * Adds a data with the given key to the hash. If entry with the given
+ * key is already in the hash, this current entry is instered before it
+ * in the collision list.
+ * Function returns iterator pointing to the inserted item in the hash.
+ */
+drm_private struct util_hash_iter
+util_hash_insert(struct util_hash *hash, unsigned key, void *data);
+
+/**
+ * Removes the item pointed to by the current iterator from the hash.
+ * Note that the data itself is not erased and if it was a malloc'ed pointer
+ * it will have to be freed after calling this function by the callee.
+ * Function returns iterator pointing to the item after the removed one in
+ * the hash.
+ */
+drm_private struct util_hash_iter
+util_hash_erase(struct util_hash *hash, struct util_hash_iter iter);
+
+drm_private void *util_hash_take(struct util_hash *hash, unsigned key);
+
+
+drm_private struct util_hash_iter util_hash_first_node(struct util_hash *hash);
+
+/**
+ * Return an iterator pointing to the first entry in the collision list.
+ */
+drm_private struct util_hash_iter
+util_hash_find(struct util_hash *hash, unsigned key);
+
+
+drm_private int util_hash_iter_is_null(struct util_hash_iter iter);
+drm_private unsigned util_hash_iter_key(struct util_hash_iter iter);
+drm_private void *util_hash_iter_data(struct util_hash_iter iter);
+
+
+drm_private struct util_hash_iter
+util_hash_iter_next(struct util_hash_iter iter);
+
+#endif
diff --git a/amdgpu/util_hash_table.c b/amdgpu/util_hash_table.c
new file mode 100644
index 0000000..89a8bf9
--- /dev/null
+++ b/amdgpu/util_hash_table.c
@@ -0,0 +1,258 @@
+/**************************************************************************
+ *
+ * Copyright 2008 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/**
+ * @file
+ * General purpose hash table implementation.
+ *
+ * Just uses the util_hash for now, but it might be better switch to a linear
+ * probing hash table implementation at some point -- as it is said they have
+ * better lookup and cache performance and it appears to be possible to write
+ * a lock-free implementation of such hash tables .
+ *
+ * @author José Fonseca <jfonseca@vmware.com>
+ */
+
+
+#include "util_hash_table.h"
+#include "util_hash.h"
+
+#include <stdlib.h>
+#include <assert.h>
+
+struct util_hash_table
+{
+ struct util_hash *head;
+
+ /** Hash function */
+ unsigned (*make_hash)(void *key);
+
+ /** Compare two keys */
+ int (*compare)(void *key1, void *key2);
+};
+
+struct util_hash_table_item
+{
+ void *key;
+ void *value;
+};
+
+
+static struct util_hash_table_item *
+util_hash_table_item(struct util_hash_iter iter)
+{
+ return (struct util_hash_table_item *)util_hash_iter_data(iter);
+}
+
+drm_private struct util_hash_table *
+util_hash_table_create(unsigned (*hash)(void *key),
+ int (*compare)(void *key1, void *key2))
+{
+ struct util_hash_table *ht;
+
+ ht = malloc(sizeof(struct util_hash_table));
+ if(!ht)
+ return NULL;
+
+ ht->head = util_hash_create();
+ if(!ht->head) {
+ free(ht);
+ return NULL;
+ }
+
+ ht->make_hash = hash;
+ ht->compare = compare;
+
+ return ht;
+}
+
+static struct util_hash_iter
+util_hash_table_find_iter(struct util_hash_table *ht,
+ void *key, unsigned key_hash)
+{
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ iter = util_hash_find(ht->head, key_hash);
+ while (!util_hash_iter_is_null(iter)) {
+ item = (struct util_hash_table_item *)util_hash_iter_data(iter);
+ if (!ht->compare(item->key, key))
+ break;
+ iter = util_hash_iter_next(iter);
+ }
+
+ return iter;
+}
+
+static struct util_hash_table_item *
+util_hash_table_find_item(struct util_hash_table *ht,
+ void *key, unsigned key_hash)
+{
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ iter = util_hash_find(ht->head, key_hash);
+ while (!util_hash_iter_is_null(iter)) {
+ item = (struct util_hash_table_item *)util_hash_iter_data(iter);
+ if (!ht->compare(item->key, key))
+ return item;
+ iter = util_hash_iter_next(iter);
+ }
+
+ return NULL;
+}
+
+drm_private void
+util_hash_table_set(struct util_hash_table *ht, void *key, void *value)
+{
+ unsigned key_hash;
+ struct util_hash_table_item *item;
+ struct util_hash_iter iter;
+
+ assert(ht);
+ if (!ht)
+ return;
+
+ key_hash = ht->make_hash(key);
+
+ item = util_hash_table_find_item(ht, key, key_hash);
+ if(item) {
+ /* TODO: key/value destruction? */
+ item->value = value;
+ return;
+ }
+
+ item = malloc(sizeof(struct util_hash_table_item));
+ if(!item)
+ return;
+
+ item->key = key;
+ item->value = value;
+
+ iter = util_hash_insert(ht->head, key_hash, item);
+ if(util_hash_iter_is_null(iter)) {
+ free(item);
+ return;
+ }
+}
+
+drm_private void *util_hash_table_get(struct util_hash_table *ht, void *key)
+{
+ unsigned key_hash;
+ struct util_hash_table_item *item;
+
+ assert(ht);
+ if (!ht)
+ return NULL;
+
+ key_hash = ht->make_hash(key);
+
+ item = util_hash_table_find_item(ht, key, key_hash);
+ if(!item)
+ return NULL;
+
+ return item->value;
+}
+
+drm_private void util_hash_table_remove(struct util_hash_table *ht, void *key)
+{
+ unsigned key_hash;
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ assert(ht);
+ if (!ht)
+ return;
+
+ key_hash = ht->make_hash(key);
+
+ iter = util_hash_table_find_iter(ht, key, key_hash);
+ if(util_hash_iter_is_null(iter))
+ return;
+
+ item = util_hash_table_item(iter);
+ assert(item);
+ free(item);
+
+ util_hash_erase(ht->head, iter);
+}
+
+drm_private void util_hash_table_clear(struct util_hash_table *ht)
+{
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ assert(ht);
+ if (!ht)
+ return;
+
+ iter = util_hash_first_node(ht->head);
+ while (!util_hash_iter_is_null(iter)) {
+ item = (struct util_hash_table_item *)util_hash_take(ht->head, util_hash_iter_key(iter));
+ free(item);
+ iter = util_hash_first_node(ht->head);
+ }
+}
+
+drm_private void util_hash_table_foreach(struct util_hash_table *ht,
+ void (*callback)(void *key, void *value, void *data),
+ void *data)
+{
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ assert(ht);
+ if (!ht)
+ return;
+
+ iter = util_hash_first_node(ht->head);
+ while (!util_hash_iter_is_null(iter)) {
+ item = (struct util_hash_table_item *)util_hash_iter_data(iter);
+ callback(item->key, item->value, data);
+ iter = util_hash_iter_next(iter);
+ }
+}
+
+drm_private void util_hash_table_destroy(struct util_hash_table *ht)
+{
+ struct util_hash_iter iter;
+ struct util_hash_table_item *item;
+
+ assert(ht);
+ if (!ht)
+ return;
+
+ iter = util_hash_first_node(ht->head);
+ while (!util_hash_iter_is_null(iter)) {
+ item = (struct util_hash_table_item *)util_hash_iter_data(iter);
+ free(item);
+ iter = util_hash_iter_next(iter);
+ }
+
+ util_hash_delete(ht->head);
+ free(ht);
+}
diff --git a/amdgpu/util_hash_table.h b/amdgpu/util_hash_table.h
new file mode 100644
index 0000000..5e295a8
--- /dev/null
+++ b/amdgpu/util_hash_table.h
@@ -0,0 +1,69 @@
+/**************************************************************************
+ *
+ * Copyright 2008 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/**
+ * General purpose hash table.
+ *
+ * @author José Fonseca <jfonseca@vmware.com>
+ */
+
+#ifndef U_HASH_TABLE_H_
+#define U_HASH_TABLE_H_
+
+#include "libdrm_macros.h"
+
+/**
+ * Generic purpose hash table.
+ */
+struct util_hash_table;
+
+/**
+ * Create an hash table.
+ *
+ * @param hash hash function
+ * @param compare should return 0 for two equal keys.
+ */
+drm_private struct util_hash_table *
+util_hash_table_create(unsigned (*hash)(void *key),
+ int (*compare)(void *key1, void *key2));
+
+drm_private void
+util_hash_table_set(struct util_hash_table *ht, void *key, void *value);
+
+drm_private void *util_hash_table_get(struct util_hash_table *ht, void *key);
+
+drm_private void util_hash_table_remove(struct util_hash_table *ht, void *key);
+
+drm_private void util_hash_table_clear(struct util_hash_table *ht);
+
+drm_private void util_hash_table_foreach(struct util_hash_table *ht,
+ void (*callback)(void *key, void *value, void *data),
+ void *data);
+
+drm_private void util_hash_table_destroy(struct util_hash_table *ht);
+
+#endif /* U_HASH_TABLE_H_ */
diff --git a/android/gralloc_handle.h b/android/gralloc_handle.h
index d3d975e..bcf753d 100644
--- a/android/gralloc_handle.h
+++ b/android/gralloc_handle.h
@@ -60,16 +60,16 @@
uint32_t usage; /* android libhardware usage flags */
uint32_t stride; /* the stride in bytes */
- int data_owner; /* owner of data (for validation) */
- uint64_t modifier __attribute__((aligned(8))); /* buffer modifiers */
+ uint64_t modifier; /* buffer modifiers */
+ int data_owner; /* owner of data (for validation) */
union {
void *data; /* pointer to struct gralloc_gbm_bo_t */
uint64_t reserved;
} __attribute__((aligned(8)));
};
-#define GRALLOC_HANDLE_VERSION 4
+#define GRALLOC_HANDLE_VERSION 3
#define GRALLOC_HANDLE_MAGIC 0x60585350
#define GRALLOC_HANDLE_NUM_FDS 1
#define GRALLOC_HANDLE_NUM_INTS ( \
diff --git a/configure.ac b/configure.ac
index 1cf9134..98a350c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.99],
+ [2.4.91],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
@@ -148,6 +148,11 @@
[Enable support for Tegra's experimental API (default: disabled)]),
[TEGRA=$enableval], [TEGRA=no])
+AC_ARG_ENABLE(rockchip-experimental-api,
+ AS_HELP_STRING([--enable-rockchip-experimental-api],
+ [Enable support for rockchip's experimental API (default: disabled)]),
+ [ROCKCHIP=$enableval], [ROCKCHIP=no])
+
AC_ARG_ENABLE(vc4,
AS_HELP_STRING([--disable-vc4],
[Enable support for vc4's API (default: auto, enabled on arm)]),
@@ -448,6 +453,11 @@
AM_CONDITIONAL(HAVE_TEGRA, [test "x$TEGRA" = xyes])
+AM_CONDITIONAL(HAVE_ROCKCHIP, [test "x$ROCKCHIP" = xyes])
+if test "x$ROCKCHIP" = xyes; then
+ AC_DEFINE(HAVE_ROCKCHIP, 1, [Have ROCKCHIP support])
+fi
+
AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes])
if test "x$VC4" = xyes; then
AC_DEFINE(HAVE_VC4, 1, [Have VC4 support])
@@ -541,7 +551,7 @@
AC_DEFINE(HAVE_VISIBILITY, 0)
fi
-CPPFLAGS="$CPPFLAGS -include config.h"
+CFLAGS="$CFLAGS -include config.h"
AC_SUBST(WARN_CFLAGS)
AC_CONFIG_FILES([
@@ -565,6 +575,8 @@
freedreno/libdrm_freedreno.pc
tegra/Makefile
tegra/libdrm_tegra.pc
+ rockchip/Makefile
+ rockchip/libdrm_rockchip.pc
vc4/Makefile
vc4/libdrm_vc4.pc
etnaviv/Makefile
@@ -581,6 +593,7 @@
tests/exynos/Makefile
tests/tegra/Makefile
tests/nouveau/Makefile
+ tests/planetest/Makefile
tests/etnaviv/Makefile
tests/util/Makefile
man/Makefile
@@ -600,6 +613,7 @@
echo " EXYNOS API $EXYNOS"
echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)"
echo " Tegra API $TEGRA"
+echo " Rockchip API $ROCKCHIP"
echo " VC4 API $VC4"
echo " Etnaviv API $ETNAVIV"
echo ""
diff --git a/data/amdgpu.ids b/data/amdgpu.ids
index f61497e..1828e41 100644
--- a/data/amdgpu.ids
+++ b/data/amdgpu.ids
@@ -4,10 +4,6 @@
# device_id, revision_id, product_name <-- single tab after comma
1.0.0
-15DD, 81, AMD Ryzen Embedded V1807B with Radeon Vega Gfx
-15DD, 82, AMD Ryzen Embedded V1756B with Radeon Vega Gfx
-15DD, 83, AMD Ryzen Embedded V1605B with Radeon Vega Gfx
-15DD, 85, AMD Ryzen Embedded V1202B with Radeon Vega Gfx
6600, 0, AMD Radeon HD 8600/8700M
6600, 81, AMD Radeon (TM) R7 M370
6601, 0, AMD Radeon (TM) HD 8500M/8700M
@@ -45,7 +41,6 @@
6665, 83, AMD Radeon (TM) R5 M320
6667, 0, AMD Radeon R5 M200 Series
666F, 0, AMD Radeon HD 8500M
-66AF, C1, AMD Radeon VII
6780, 0, ATI FirePro V (FireGL V) Graphics Adapter
678A, 0, ATI FirePro V (FireGL V) Graphics Adapter
6798, 0, AMD Radeon HD 7900 Series
@@ -68,12 +63,9 @@
67DF, C7, AMD Radeon (TM) RX 480 Graphics
67DF, CF, AMD Radeon (TM) RX 470 Graphics
67DF, D7, Radeon(TM) RX 470 Graphics
-67DF, E0, Radeon RX 470 Series
-67DF, E1, Radeon RX 590 Series
67DF, E3, Radeon RX Series
67DF, E7, Radeon RX 580 Series
67DF, EF, Radeon RX 570 Series
-67DF, F7, Radeon RX P30PH
67C2, 01, AMD Radeon (TM) Pro V7350x2
67C2, 02, AMD Radeon (TM) Pro V7300X
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
@@ -93,7 +85,6 @@
67EF, C5, AMD Radeon (TM) RX 460 Graphics
67EF, C7, AMD Radeon (TM) RX Graphics
67EF, CF, AMD Radeon (TM) RX 460 Graphics
-67EF, E2, RX 560X
67EF, E0, Radeon RX 560 Series
67EF, E1, Radeon RX Series
67EF, E3, Radeon RX Series
@@ -136,23 +127,21 @@
683D, 0, AMD Radeon HD 7700 Series
683F, 0, AMD Radeon HD 7700 Series
6860, 00, Radeon Instinct MI25
-6860, 01, Radeon Instinct MI25
+6860, 01, Radeon Pro V320
6860, 02, Radeon Instinct MI25
6860, 03, Radeon Pro V340
6860, 04, Radeon Instinct MI25x2
-6861, 00, Radeon Pro WX 9100
+6861, 00, Radeon(TM) Pro WX9100
6862, 00, Radeon Pro SSG
6863, 00, Radeon Vega Frontier Edition
6864, 03, Radeon Pro V340
6864, 04, Instinct MI25x2
-6868, 00, Radeon (TM) PRO WX 8200
-686C, 00, Radeon Instinct MI25 MxGPU
-686C, 01, Radeon Instinct MI25 MxGPU
-686C, 02, Radeon Instinct MI25 MxGPU
-686C, 03, Radeon Pro V340 MxGPU
-686C, 04, Radeon Instinct MI25x2 MxGPU
-686C, 05, Radeon Pro V340L MxGPU
-686C, 06, Radeon Instinct MI25 MxGPU
+6868, 00, Radeon(TM) Pro WX8100
+686C, 00, GLXT (Radeon Instinct MI25) MxGPU VFID
+686C, 01, GLXT (Radeon Pro V320) MxGPU
+686C, 02, GLXT (Radeon Instinct MI25) MxGPU
+686C, 03, GLXT (Radeon Pro V340) MxGPU
+686C, 04, GLXT (Radeon Instinct MI25x2) MxGPU
687F, C0, Radeon RX Vega
687F, C1, Radeon RX Vega
687F, C3, Radeon RX Vega
@@ -176,15 +165,12 @@
6980, 00, Radeon Pro WX3100
6985, 00, AMD Radeon Pro WX3100
6987, 80, AMD Embedded Radeon E9171
-6987, C0, Radeon 550X Series
-6987, C3, Radeon 540X Series
6995, 00, AMD Radeon Pro WX2100
6997, 00, Radeon Pro WX2100
699F, 81, AMD Embedded Radeon E9170 Series
699F, C0, Radeon 500 Series
-699F, C1, Radeon 540 Series
699F, C3, Radeon 500 Series
-699F, C7, Radeon 550 Series
+699F, C7, Radeon RX 550 Series
7300, C1, AMD FirePro (TM) S9300 x2
7300, C8, AMD Radeon (TM) R9 Fury Series
7300, C9, Radeon (TM) Pro Duo
@@ -199,4 +185,3 @@
9874, 87, AMD Radeon R5 Graphics
9874, 85, AMD Radeon R6 Graphics
9874, 84, AMD Radeon R7 Graphics
-6FDF, EF, AMD Radeon RX 580 2048SP
diff --git a/etnaviv/Makefile.am b/etnaviv/Makefile.am
index 648e3c5..be96ba8 100644
--- a/etnaviv/Makefile.am
+++ b/etnaviv/Makefile.am
@@ -2,7 +2,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
@@ -23,6 +22,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_etnaviv.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = etnaviv-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/etnaviv/etnaviv-symbol-check b/etnaviv/etnaviv-symbol-check
index 6f6a7a2..bc50961 100755
--- a/etnaviv/etnaviv-symbol-check
+++ b/etnaviv/etnaviv-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_ETNAVIV_H_FILES
@@ -25,6 +23,7 @@
etna_pipe_wait
etna_pipe_wait_ns
etna_bo_new
+etna_bo_from_handle
etna_bo_from_name
etna_bo_from_dmabuf
etna_bo_ref
diff --git a/etnaviv/etnaviv_bo.c b/etnaviv/etnaviv_bo.c
index 43ce6b4..32f7b34 100644
--- a/etnaviv/etnaviv_bo.c
+++ b/etnaviv/etnaviv_bo.c
@@ -104,7 +104,7 @@
}
/* allocate a new (un-tiled) buffer object */
-drm_public struct etna_bo *etna_bo_new(struct etna_device *dev, uint32_t size,
+struct etna_bo *etna_bo_new(struct etna_device *dev, uint32_t size,
uint32_t flags)
{
struct etna_bo *bo;
@@ -131,7 +131,7 @@
return bo;
}
-drm_public struct etna_bo *etna_bo_ref(struct etna_bo *bo)
+struct etna_bo *etna_bo_ref(struct etna_bo *bo)
{
atomic_inc(&bo->refcnt);
@@ -159,8 +159,7 @@
}
/* import a buffer object from DRI2 name */
-drm_public struct etna_bo *etna_bo_from_name(struct etna_device *dev,
- uint32_t name)
+struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name)
{
struct etna_bo *bo;
struct drm_gem_open req = {
@@ -197,7 +196,7 @@
* fd so caller should close() the fd when it is otherwise done
* with it (even if it is still using the 'struct etna_bo *')
*/
-drm_public struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd)
+struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd)
{
struct etna_bo *bo;
int ret, size;
@@ -232,7 +231,7 @@
}
/* destroy a buffer object */
-drm_public void etna_bo_del(struct etna_bo *bo)
+void etna_bo_del(struct etna_bo *bo)
{
struct etna_device *dev = bo->dev;
@@ -254,7 +253,7 @@
}
/* get the global flink/DRI2 buffer name */
-drm_public int etna_bo_get_name(struct etna_bo *bo, uint32_t *name)
+int etna_bo_get_name(struct etna_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@@ -278,7 +277,7 @@
return 0;
}
-drm_public uint32_t etna_bo_handle(struct etna_bo *bo)
+uint32_t etna_bo_handle(struct etna_bo *bo)
{
return bo->handle;
}
@@ -286,7 +285,7 @@
/* caller owns the dmabuf fd that is returned and is responsible
* to close() it when done
*/
-drm_public int etna_bo_dmabuf(struct etna_bo *bo)
+int etna_bo_dmabuf(struct etna_bo *bo)
{
int ret, prime_fd;
@@ -302,12 +301,12 @@
return prime_fd;
}
-drm_public uint32_t etna_bo_size(struct etna_bo *bo)
+uint32_t etna_bo_size(struct etna_bo *bo)
{
return bo->size;
}
-drm_public void *etna_bo_map(struct etna_bo *bo)
+void *etna_bo_map(struct etna_bo *bo)
{
if (!bo->map) {
if (!bo->offset) {
@@ -325,7 +324,7 @@
return bo->map;
}
-drm_public int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
+int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op)
{
struct drm_etnaviv_gem_cpu_prep req = {
.handle = bo->handle,
@@ -338,7 +337,7 @@
&req, sizeof(req));
}
-drm_public void etna_bo_cpu_fini(struct etna_bo *bo)
+void etna_bo_cpu_fini(struct etna_bo *bo)
{
struct drm_etnaviv_gem_cpu_fini req = {
.handle = bo->handle,
diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c
index 261777b..1373016 100644
--- a/etnaviv/etnaviv_cmd_stream.c
+++ b/etnaviv/etnaviv_cmd_stream.c
@@ -55,8 +55,7 @@
return (struct etna_cmd_stream_priv *)stream;
}
-drm_public struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe,
- uint32_t size,
+struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
void *priv)
{
@@ -96,7 +95,7 @@
return NULL;
}
-drm_public void etna_cmd_stream_del(struct etna_cmd_stream *stream)
+void etna_cmd_stream_del(struct etna_cmd_stream *stream)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
@@ -120,7 +119,7 @@
priv->reset_notify(stream, priv->reset_notify_priv);
}
-drm_public uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream)
+uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream)
{
return etna_cmd_stream_priv(stream)->last_timestamp;
}
@@ -150,7 +149,11 @@
pthread_mutex_lock(&idx_lock);
- if (bo->current_stream == stream) {
+ if (!bo->current_stream) {
+ idx = append_bo(stream, bo);
+ bo->current_stream = stream;
+ bo->idx = idx;
+ } else if (bo->current_stream == stream) {
idx = bo->idx;
} else {
/* slow-path: */
@@ -161,8 +164,6 @@
/* not found */
idx = append_bo(stream, bo);
}
- bo->current_stream = stream;
- bo->idx = idx;
}
pthread_mutex_unlock(&idx_lock);
@@ -221,21 +222,20 @@
*out_fence_fd = req.fence_fd;
}
-drm_public void etna_cmd_stream_flush(struct etna_cmd_stream *stream)
+void etna_cmd_stream_flush(struct etna_cmd_stream *stream)
{
flush(stream, -1, NULL);
reset_buffer(stream);
}
-drm_public void etna_cmd_stream_flush2(struct etna_cmd_stream *stream,
- int in_fence_fd,
- int *out_fence_fd)
+void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd,
+ int *out_fence_fd)
{
flush(stream, in_fence_fd, out_fence_fd);
reset_buffer(stream);
}
-drm_public void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
+void etna_cmd_stream_finish(struct etna_cmd_stream *stream)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
@@ -244,8 +244,7 @@
reset_buffer(stream);
}
-drm_public void etna_cmd_stream_reloc(struct etna_cmd_stream *stream,
- const struct etna_reloc *r)
+void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
struct drm_etnaviv_gem_submit_reloc *reloc;
@@ -262,7 +261,7 @@
etna_cmd_stream_emit(stream, addr);
}
-drm_public void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p)
+void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p)
{
struct etna_cmd_stream_priv *priv = etna_cmd_stream_priv(stream);
struct drm_etnaviv_gem_submit_pmr *pmr;
diff --git a/etnaviv/etnaviv_device.c b/etnaviv/etnaviv_device.c
index 699df25..d83e8d3 100644
--- a/etnaviv/etnaviv_device.c
+++ b/etnaviv/etnaviv_device.c
@@ -41,7 +41,7 @@
static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER;
-drm_public struct etna_device *etna_device_new(int fd)
+struct etna_device *etna_device_new(int fd)
{
struct etna_device *dev = calloc(sizeof(*dev), 1);
@@ -59,7 +59,7 @@
/* like etna_device_new() but creates it's own private dup() of the fd
* which is close()d when the device is finalized. */
-drm_public struct etna_device *etna_device_new_dup(int fd)
+struct etna_device *etna_device_new_dup(int fd)
{
int dup_fd = dup(fd);
struct etna_device *dev = etna_device_new(dup_fd);
@@ -72,7 +72,7 @@
return dev;
}
-drm_public struct etna_device *etna_device_ref(struct etna_device *dev)
+struct etna_device *etna_device_ref(struct etna_device *dev)
{
atomic_inc(&dev->refcnt);
@@ -99,7 +99,7 @@
etna_device_del_impl(dev);
}
-drm_public void etna_device_del(struct etna_device *dev)
+void etna_device_del(struct etna_device *dev)
{
if (!atomic_dec_and_test(&dev->refcnt))
return;
@@ -109,7 +109,7 @@
pthread_mutex_unlock(&table_lock);
}
-drm_public int etna_device_fd(struct etna_device *dev)
+int etna_device_fd(struct etna_device *dev)
{
return dev->fd;
}
diff --git a/etnaviv/etnaviv_drmif.h b/etnaviv/etnaviv_drmif.h
index 80aedc1..5a6bef8 100644
--- a/etnaviv/etnaviv_drmif.h
+++ b/etnaviv/etnaviv_drmif.h
@@ -115,6 +115,8 @@
struct etna_bo *etna_bo_new(struct etna_device *dev,
uint32_t size, uint32_t flags);
+struct etna_bo *etna_bo_from_handle(struct etna_device *dev,
+ uint32_t handle, uint32_t size);
struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
struct etna_bo *etna_bo_ref(struct etna_bo *bo);
diff --git a/etnaviv/etnaviv_gpu.c b/etnaviv/etnaviv_gpu.c
index dc4c126..f7efa02 100644
--- a/etnaviv/etnaviv_gpu.c
+++ b/etnaviv/etnaviv_gpu.c
@@ -44,7 +44,7 @@
return req.value;
}
-drm_public struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core)
+struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core)
{
struct etna_gpu *gpu;
@@ -73,12 +73,12 @@
return NULL;
}
-drm_public void etna_gpu_del(struct etna_gpu *gpu)
+void etna_gpu_del(struct etna_gpu *gpu)
{
free(gpu);
}
-drm_public int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
+int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
uint64_t *value)
{
struct etna_device *dev = gpu->dev;
diff --git a/etnaviv/etnaviv_perfmon.c b/etnaviv/etnaviv_perfmon.c
index f6576b8..5f408a7 100644
--- a/etnaviv/etnaviv_perfmon.c
+++ b/etnaviv/etnaviv_perfmon.c
@@ -121,7 +121,7 @@
}
}
-drm_public struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe)
+struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe)
{
struct etna_perfmon *pm;
int ret;
@@ -147,7 +147,7 @@
return NULL;
}
-drm_public void etna_perfmon_del(struct etna_perfmon *pm)
+void etna_perfmon_del(struct etna_perfmon *pm)
{
if (!pm)
return;
@@ -156,7 +156,7 @@
free(pm);
}
-drm_public struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name)
+struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name)
{
struct etna_perfmon_domain *dom;
@@ -170,7 +170,7 @@
return NULL;
}
-drm_public struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name)
+struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name)
{
struct etna_perfmon_signal *signal;
diff --git a/etnaviv/etnaviv_pipe.c b/etnaviv/etnaviv_pipe.c
index 4120a36..53954aa 100644
--- a/etnaviv/etnaviv_pipe.c
+++ b/etnaviv/etnaviv_pipe.c
@@ -26,12 +26,12 @@
#include "etnaviv_priv.h"
-drm_public int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms)
+int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms)
{
return etna_pipe_wait_ns(pipe, timestamp, ms * 1000000);
}
-drm_public int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns)
+int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns)
{
struct etna_device *dev = pipe->gpu->dev;
int ret;
@@ -55,12 +55,12 @@
return 0;
}
-drm_public void etna_pipe_del(struct etna_pipe *pipe)
+void etna_pipe_del(struct etna_pipe *pipe)
{
free(pipe);
}
-drm_public struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id)
+struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id)
{
struct etna_pipe *pipe;
diff --git a/etnaviv/etnaviv_priv.h b/etnaviv/etnaviv_priv.h
index eef7f49..e45d364 100644
--- a/etnaviv/etnaviv_priv.h
+++ b/etnaviv/etnaviv_priv.h
@@ -150,7 +150,7 @@
struct etna_bo **bos;
uint32_t nr_bos, max_bos;
- /* notify callback if buffer reset happened */
+ /* notify callback if buffer reset happend */
void (*reset_notify)(struct etna_cmd_stream *stream, void *priv);
void *reset_notify_priv;
};
diff --git a/etnaviv/meson.build b/etnaviv/meson.build
index 515a4ed..ca2aa54 100644
--- a/etnaviv/meson.build
+++ b/etnaviv/meson.build
@@ -30,7 +30,7 @@
],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
dependencies : [dep_pthread_stubs, dep_rt, dep_atomic_ops],
version : '1.0.0',
install : true,
diff --git a/exynos/Makefile.am b/exynos/Makefile.am
index 76b185d..f99f898 100644
--- a/exynos/Makefile.am
+++ b/exynos/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
@@ -24,6 +23,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_exynos.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = exynos-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/exynos/exynos-symbol-check b/exynos/exynos-symbol-check
index 49d611e..e9f1b04 100755
--- a/exynos/exynos-symbol-check
+++ b/exynos/exynos-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.am/libdrm_exynos*_HEADERS
diff --git a/exynos/exynos_drm.c b/exynos/exynos_drm.c
index b008ad7..e1afef6 100644
--- a/exynos/exynos_drm.c
+++ b/exynos/exynos_drm.c
@@ -48,7 +48,7 @@
*
* if true, return the device object else NULL.
*/
-drm_public struct exynos_device * exynos_device_create(int fd)
+struct exynos_device * exynos_device_create(int fd)
{
struct exynos_device *dev;
@@ -69,7 +69,7 @@
*
* @dev: exynos drm device object.
*/
-drm_public void exynos_device_destroy(struct exynos_device *dev)
+void exynos_device_destroy(struct exynos_device *dev)
{
free(dev);
}
@@ -87,8 +87,8 @@
*
* if true, return a exynos buffer object else NULL.
*/
-drm_public struct exynos_bo * exynos_bo_create(struct exynos_device *dev,
- size_t size, uint32_t flags)
+struct exynos_bo * exynos_bo_create(struct exynos_device *dev,
+ size_t size, uint32_t flags)
{
struct exynos_bo *bo;
struct drm_exynos_gem_create req = {
@@ -141,8 +141,8 @@
*
* if true, return 0 else negative.
*/
-drm_public int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle,
- size_t *size, uint32_t *flags)
+int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle,
+ size_t *size, uint32_t *flags)
{
int ret;
struct drm_exynos_gem_info req = {
@@ -167,7 +167,7 @@
*
* @bo: a exynos buffer object to be destroyed.
*/
-drm_public void exynos_bo_destroy(struct exynos_bo *bo)
+void exynos_bo_destroy(struct exynos_bo *bo)
{
if (!bo)
return;
@@ -199,7 +199,7 @@
* if true, return a exynos buffer object else NULL.
*
*/
-drm_public struct exynos_bo *
+struct exynos_bo *
exynos_bo_from_name(struct exynos_device *dev, uint32_t name)
{
struct exynos_bo *bo;
@@ -242,7 +242,7 @@
*
* if true, return 0 else negative.
*/
-drm_public int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name)
+int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@@ -265,7 +265,7 @@
return 0;
}
-drm_public uint32_t exynos_bo_handle(struct exynos_bo *bo)
+uint32_t exynos_bo_handle(struct exynos_bo *bo)
{
return bo->handle;
}
@@ -276,9 +276,9 @@
* @bo: a exynos buffer object including a gem object handle to be mmapped
* to user space.
*
- * if true, user pointer mmapped else NULL.
+ * if true, user pointer mmaped else NULL.
*/
-drm_public void *exynos_bo_map(struct exynos_bo *bo)
+void *exynos_bo_map(struct exynos_bo *bo)
{
if (!bo->vaddr) {
struct exynos_device *dev = bo->dev;
@@ -315,7 +315,7 @@
*
* @return: 0 on success, -1 on error, and errno will be set
*/
-drm_public int
+int
exynos_prime_handle_to_fd(struct exynos_device *dev, uint32_t handle, int *fd)
{
return drmPrimeHandleToFD(dev->fd, handle, 0, fd);
@@ -330,7 +330,7 @@
*
* @return: 0 on success, -1 on error, and errno will be set
*/
-drm_public int
+int
exynos_prime_fd_to_handle(struct exynos_device *dev, int fd, uint32_t *handle)
{
return drmPrimeFDToHandle(dev->fd, fd, handle);
@@ -353,7 +353,7 @@
*
* if true, return 0 else negative.
*/
-drm_public int
+int
exynos_vidi_connection(struct exynos_device *dev, uint32_t connect,
uint32_t ext, void *edid)
{
@@ -394,7 +394,7 @@
}
}
-drm_public int
+int
exynos_handle_event(struct exynos_device *dev, struct exynos_event_context *ctx)
{
char buffer[1024];
diff --git a/exynos/exynos_drm.h b/exynos/exynos_drm.h
index 50181c4..c3af0ac 100644
--- a/exynos/exynos_drm.h
+++ b/exynos/exynos_drm.h
@@ -64,7 +64,7 @@
/**
* A structure for user connection request of virtual display.
*
- * @connection: indicate whether doing connection or not by user.
+ * @connection: indicate whether doing connetion or not by user.
* @extensions: if this value is 1 then the vidi driver would need additional
* 128bytes edid data.
* @edid: the edid data pointer from user side.
diff --git a/exynos/exynos_drmif.h b/exynos/exynos_drmif.h
index bcf8595..154439b 100644
--- a/exynos/exynos_drmif.h
+++ b/exynos/exynos_drmif.h
@@ -46,7 +46,7 @@
* @handle: a gem handle to gem object created.
* @flags: indicate memory allocation and cache attribute types.
* @size: size to the buffer created.
- * @vaddr: user space address to a gem buffer mmapped.
+ * @vaddr: user space address to a gem buffer mmaped.
* @name: a gem global handle from flink request.
*/
struct exynos_bo {
diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c
index ac6fa68..bca884b 100644
--- a/exynos/exynos_fimg2d.c
+++ b/exynos/exynos_fimg2d.c
@@ -356,7 +356,7 @@
*
* fd: a file descriptor to an opened drm device.
*/
-drm_public struct g2d_context *g2d_init(int fd)
+struct g2d_context *g2d_init(int fd)
{
struct drm_exynos_g2d_get_ver ver;
struct g2d_context *ctx;
@@ -384,7 +384,7 @@
return ctx;
}
-drm_public void g2d_fini(struct g2d_context *ctx)
+void g2d_fini(struct g2d_context *ctx)
{
free(ctx);
}
@@ -400,7 +400,7 @@
* @ctx: a pointer to g2d_context structure.
* @userdata: a pointer to the user data
*/
-drm_public void g2d_config_event(struct g2d_context *ctx, void *userdata)
+void g2d_config_event(struct g2d_context *ctx, void *userdata)
{
ctx->event_userdata = userdata;
}
@@ -410,7 +410,7 @@
*
* @ctx: a pointer to g2d_context structure.
*/
-drm_public int g2d_exec(struct g2d_context *ctx)
+int g2d_exec(struct g2d_context *ctx)
{
struct drm_exynos_g2d_exec exec;
int ret;
@@ -442,7 +442,7 @@
* @w: width value to buffer filled with given color data.
* @h: height value to buffer filled with given color data.
*/
-drm_public int
+int
g2d_solid_fill(struct g2d_context *ctx, struct g2d_image *img,
unsigned int x, unsigned int y, unsigned int w,
unsigned int h)
@@ -495,7 +495,7 @@
* @w: width value to source and destination buffers.
* @h: height value to source and destination buffers.
*/
-drm_public int
+int
g2d_copy(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x, unsigned int src_y,
unsigned int dst_x, unsigned dst_y, unsigned int w,
@@ -578,7 +578,7 @@
* @w: width of rectangle to move.
* @h: height of rectangle to move.
*/
-drm_public int
+int
g2d_move(struct g2d_context *ctx, struct g2d_image *img,
unsigned int src_x, unsigned int src_y,
unsigned int dst_x, unsigned dst_y, unsigned int w,
@@ -676,7 +676,7 @@
* @negative: indicate that it uses color negative to source and
* destination buffers.
*/
-drm_public int
+int
g2d_copy_with_scale(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x,
unsigned int src_y, unsigned int src_w,
@@ -785,7 +785,7 @@
* @h: height value to source and destination buffer.
* @op: blend operation type.
*/
-drm_public int
+int
g2d_blend(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x,
unsigned int src_y, unsigned int dst_x, unsigned int dst_y,
@@ -902,7 +902,7 @@
* @dst_h: height value to destination buffer.
* @op: blend operation type.
*/
-drm_public int
+int
g2d_scale_and_blend(struct g2d_context *ctx, struct g2d_image *src,
struct g2d_image *dst, unsigned int src_x, unsigned int src_y,
unsigned int src_w, unsigned int src_h, unsigned int dst_x,
diff --git a/exynos/meson.build b/exynos/meson.build
index bdfc3fc..30d3640 100644
--- a/exynos/meson.build
+++ b/exynos/meson.build
@@ -21,7 +21,7 @@
libdrm_exynos = shared_library(
'drm_exynos',
[files('exynos_drm.c', 'exynos_fimg2d.c'), config_file],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs],
diff --git a/freedreno/Makefile.am b/freedreno/Makefile.am
index 3784503..cbb0d03 100644
--- a/freedreno/Makefile.am
+++ b/freedreno/Makefile.am
@@ -3,7 +3,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
$(VALGRIND_CFLAGS) \
@@ -28,6 +27,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_freedreno.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = freedreno-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/freedreno/Makefile.sources b/freedreno/Makefile.sources
index ca89511..68a679b 100644
--- a/freedreno/Makefile.sources
+++ b/freedreno/Makefile.sources
@@ -7,6 +7,7 @@
freedreno_bo_cache.c \
msm/msm_bo.c \
msm/msm_device.c \
+ msm/msm_drm.h \
msm/msm_pipe.c \
msm/msm_priv.h \
msm/msm_ringbuffer.c
diff --git a/freedreno/freedreno-symbol-check b/freedreno/freedreno-symbol-check
index 978026c..3b11952 100755
--- a/freedreno/freedreno-symbol-check
+++ b/freedreno/freedreno-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_FREEDRENO_H_FILES
@@ -38,7 +36,6 @@
fd_pipe_get_param
fd_pipe_new
fd_pipe_new2
-fd_pipe_ref
fd_pipe_wait
fd_pipe_wait_timeout
fd_ringbuffer_cmd_count
@@ -48,16 +45,17 @@
fd_ringbuffer_flush
fd_ringbuffer_grow
fd_ringbuffer_new
-fd_ringbuffer_new_flags
-fd_ringbuffer_new_object
-fd_ringbuffer_ref
fd_ringbuffer_reloc
fd_ringbuffer_reloc2
fd_ringbuffer_reset
fd_ringbuffer_set_parent
-fd_ringbuffer_size
fd_ringbuffer_timestamp
+fd_ringmarker_del
+fd_ringmarker_dwords
+fd_ringmarker_flush
fd_ringbuffer_flush2
+fd_ringmarker_mark
+fd_ringmarker_new
EOF
done)
diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c
index efc5b71..34c285f 100644
--- a/freedreno/freedreno_bo.c
+++ b/freedreno/freedreno_bo.c
@@ -78,15 +78,14 @@
return bo;
}
-static struct fd_bo *
-bo_new(struct fd_device *dev, uint32_t size, uint32_t flags,
- struct fd_bo_cache *cache)
+struct fd_bo *
+fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
{
struct fd_bo *bo = NULL;
uint32_t handle;
int ret;
- bo = fd_bo_cache_alloc(cache, &size, flags);
+ bo = fd_bo_cache_alloc(&dev->bo_cache, &size, flags);
if (bo)
return bo;
@@ -96,6 +95,7 @@
pthread_mutex_lock(&table_lock);
bo = bo_from_handle(dev, size, handle);
+ bo->bo_reuse = TRUE;
pthread_mutex_unlock(&table_lock);
VG_BO_ALLOC(bo);
@@ -103,30 +103,7 @@
return bo;
}
-drm_public struct fd_bo *
-fd_bo_new(struct fd_device *dev, uint32_t size, uint32_t flags)
-{
- struct fd_bo *bo = bo_new(dev, size, flags, &dev->bo_cache);
- if (bo)
- bo->bo_reuse = BO_CACHE;
- return bo;
-}
-
-/* internal function to allocate bo's that use the ringbuffer cache
- * instead of the normal bo_cache. The purpose is, because cmdstream
- * bo's get vmap'd on the kernel side, and that is expensive, we want
- * to re-use cmdstream bo's for cmdstream and not unrelated purposes.
- */
-drm_private struct fd_bo *
-fd_bo_new_ring(struct fd_device *dev, uint32_t size, uint32_t flags)
-{
- struct fd_bo *bo = bo_new(dev, size, flags, &dev->ring_cache);
- if (bo)
- bo->bo_reuse = RING_CACHE;
- return bo;
-}
-
-drm_public struct fd_bo *
+struct fd_bo *
fd_bo_from_handle(struct fd_device *dev, uint32_t handle, uint32_t size)
{
struct fd_bo *bo = NULL;
@@ -147,7 +124,7 @@
return bo;
}
-drm_public struct fd_bo *
+struct fd_bo *
fd_bo_from_dmabuf(struct fd_device *dev, int fd)
{
int ret, size;
@@ -179,7 +156,7 @@
return bo;
}
-drm_public struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
+struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name)
{
struct drm_gem_open req = {
.name = name,
@@ -214,23 +191,23 @@
return bo;
}
-drm_public uint64_t fd_bo_get_iova(struct fd_bo *bo)
+uint64_t fd_bo_get_iova(struct fd_bo *bo)
{
return bo->funcs->iova(bo);
}
-drm_public void fd_bo_put_iova(struct fd_bo *bo)
+void fd_bo_put_iova(struct fd_bo *bo)
{
/* currently a no-op */
}
-drm_public struct fd_bo * fd_bo_ref(struct fd_bo *bo)
+struct fd_bo * fd_bo_ref(struct fd_bo *bo)
{
atomic_inc(&bo->refcnt);
return bo;
}
-drm_public void fd_bo_del(struct fd_bo *bo)
+void fd_bo_del(struct fd_bo *bo)
{
struct fd_device *dev = bo->dev;
@@ -239,9 +216,7 @@
pthread_mutex_lock(&table_lock);
- if ((bo->bo_reuse == BO_CACHE) && (fd_bo_cache_free(&dev->bo_cache, bo) == 0))
- goto out;
- if ((bo->bo_reuse == RING_CACHE) && (fd_bo_cache_free(&dev->ring_cache, bo) == 0))
+ if (bo->bo_reuse && (fd_bo_cache_free(&dev->bo_cache, bo) == 0))
goto out;
bo_del(bo);
@@ -275,7 +250,7 @@
bo->funcs->destroy(bo);
}
-drm_public int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
+int fd_bo_get_name(struct fd_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@@ -291,7 +266,7 @@
pthread_mutex_lock(&table_lock);
set_name(bo, req.name);
pthread_mutex_unlock(&table_lock);
- bo->bo_reuse = NO_CACHE;
+ bo->bo_reuse = FALSE;
}
*name = bo->name;
@@ -299,12 +274,12 @@
return 0;
}
-drm_public uint32_t fd_bo_handle(struct fd_bo *bo)
+uint32_t fd_bo_handle(struct fd_bo *bo)
{
return bo->handle;
}
-drm_public int fd_bo_dmabuf(struct fd_bo *bo)
+int fd_bo_dmabuf(struct fd_bo *bo)
{
int ret, prime_fd;
@@ -315,17 +290,17 @@
return ret;
}
- bo->bo_reuse = NO_CACHE;
+ bo->bo_reuse = FALSE;
return prime_fd;
}
-drm_public uint32_t fd_bo_size(struct fd_bo *bo)
+uint32_t fd_bo_size(struct fd_bo *bo)
{
return bo->size;
}
-drm_public void * fd_bo_map(struct fd_bo *bo)
+void * fd_bo_map(struct fd_bo *bo)
{
if (!bo->map) {
uint64_t offset;
@@ -347,18 +322,18 @@
}
/* a bit odd to take the pipe as an arg, but it's a, umm, quirk of kgsl.. */
-drm_public int fd_bo_cpu_prep(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op)
+int fd_bo_cpu_prep(struct fd_bo *bo, struct fd_pipe *pipe, uint32_t op)
{
return bo->funcs->cpu_prep(bo, pipe, op);
}
-drm_public void fd_bo_cpu_fini(struct fd_bo *bo)
+void fd_bo_cpu_fini(struct fd_bo *bo)
{
bo->funcs->cpu_fini(bo);
}
#if !HAVE_FREEDRENO_KGSL
-drm_public struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
+struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
{
return NULL;
}
diff --git a/freedreno/freedreno_bo_cache.c b/freedreno/freedreno_bo_cache.c
index bb0605a..3b73715 100644
--- a/freedreno/freedreno_bo_cache.c
+++ b/freedreno/freedreno_bo_cache.c
@@ -49,7 +49,7 @@
* fill in for a bit smoother size curve..
*/
drm_private void
-fd_bo_cache_init(struct fd_bo_cache *cache, int coarse)
+fd_bo_cache_init(struct fd_bo_cache *cache, int course)
{
unsigned long size, cache_max_size = 64 * 1024 * 1024;
@@ -63,13 +63,13 @@
*/
add_bucket(cache, 4096);
add_bucket(cache, 4096 * 2);
- if (!coarse)
+ if (!course)
add_bucket(cache, 4096 * 3);
/* Initialize the linked lists for BO reuse cache. */
for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
add_bucket(cache, size);
- if (!coarse) {
+ if (!course) {
add_bucket(cache, size + size * 1 / 4);
add_bucket(cache, size + size * 2 / 4);
add_bucket(cache, size + size * 3 / 4);
diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c
index ac23430..0b42561 100644
--- a/freedreno/freedreno_device.c
+++ b/freedreno/freedreno_device.c
@@ -38,7 +38,7 @@
struct fd_device * kgsl_device_new(int fd);
struct fd_device * msm_device_new(int fd);
-drm_public struct fd_device * fd_device_new(int fd)
+struct fd_device * fd_device_new(int fd)
{
struct fd_device *dev;
drmVersionPtr version;
@@ -82,7 +82,6 @@
dev->handle_table = drmHashCreate();
dev->name_table = drmHashCreate();
fd_bo_cache_init(&dev->bo_cache, FALSE);
- fd_bo_cache_init(&dev->ring_cache, TRUE);
return dev;
}
@@ -90,7 +89,7 @@
/* like fd_device_new() but creates it's own private dup() of the fd
* which is close()d when the device is finalized.
*/
-drm_public struct fd_device * fd_device_new_dup(int fd)
+struct fd_device * fd_device_new_dup(int fd)
{
int dup_fd = dup(fd);
struct fd_device *dev = fd_device_new(dup_fd);
@@ -101,7 +100,7 @@
return dev;
}
-drm_public struct fd_device * fd_device_ref(struct fd_device *dev)
+struct fd_device * fd_device_ref(struct fd_device *dev)
{
atomic_inc(&dev->refcnt);
return dev;
@@ -125,7 +124,7 @@
fd_device_del_impl(dev);
}
-drm_public void fd_device_del(struct fd_device *dev)
+void fd_device_del(struct fd_device *dev)
{
if (!atomic_dec_and_test(&dev->refcnt))
return;
@@ -134,12 +133,12 @@
pthread_mutex_unlock(&table_lock);
}
-drm_public int fd_device_fd(struct fd_device *dev)
+int fd_device_fd(struct fd_device *dev)
{
return dev->fd;
}
-drm_public enum fd_version fd_device_version(struct fd_device *dev)
+enum fd_version fd_device_version(struct fd_device *dev)
{
return dev->version;
}
diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h
index c95c21b..2711518 100644
--- a/freedreno/freedreno_drmif.h
+++ b/freedreno/freedreno_drmif.h
@@ -104,7 +104,6 @@
struct fd_pipe * fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id);
struct fd_pipe * fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio);
-struct fd_pipe * fd_pipe_ref(struct fd_pipe *pipe);
void fd_pipe_del(struct fd_pipe *pipe);
int fd_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param,
uint64_t *value);
diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c
index e82e644..77b160e 100644
--- a/freedreno/freedreno_pipe.c
+++ b/freedreno/freedreno_pipe.c
@@ -33,7 +33,7 @@
* priority of zero is highest priority, and higher numeric values are
* lower priorities
*/
-drm_public struct fd_pipe *
+struct fd_pipe *
fd_pipe_new2(struct fd_device *dev, enum fd_pipe_id id, uint32_t prio)
{
struct fd_pipe *pipe;
@@ -57,7 +57,6 @@
pipe->dev = dev;
pipe->id = id;
- atomic_set(&pipe->refcnt, 1);
fd_pipe_get_param(pipe, FD_GPU_ID, &val);
pipe->gpu_id = val;
@@ -65,37 +64,29 @@
return pipe;
}
-drm_public struct fd_pipe *
+struct fd_pipe *
fd_pipe_new(struct fd_device *dev, enum fd_pipe_id id)
{
return fd_pipe_new2(dev, id, 1);
}
-drm_public struct fd_pipe * fd_pipe_ref(struct fd_pipe *pipe)
+void fd_pipe_del(struct fd_pipe *pipe)
{
- atomic_inc(&pipe->refcnt);
- return pipe;
-}
-
-drm_public void fd_pipe_del(struct fd_pipe *pipe)
-{
- if (!atomic_dec_and_test(&pipe->refcnt))
- return;
pipe->funcs->destroy(pipe);
}
-drm_public int fd_pipe_get_param(struct fd_pipe *pipe,
+int fd_pipe_get_param(struct fd_pipe *pipe,
enum fd_param_id param, uint64_t *value)
{
return pipe->funcs->get_param(pipe, param, value);
}
-drm_public int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp)
+int fd_pipe_wait(struct fd_pipe *pipe, uint32_t timestamp)
{
return fd_pipe_wait_timeout(pipe, timestamp, ~0);
}
-drm_public int fd_pipe_wait_timeout(struct fd_pipe *pipe, uint32_t timestamp,
+int fd_pipe_wait_timeout(struct fd_pipe *pipe, uint32_t timestamp,
uint64_t timeout)
{
return pipe->funcs->wait(pipe, timestamp, timeout);
diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h
index b8eac4b..6c9e509 100644
--- a/freedreno/freedreno_priv.h
+++ b/freedreno/freedreno_priv.h
@@ -98,7 +98,6 @@
const struct fd_device_funcs *funcs;
struct fd_bo_cache bo_cache;
- struct fd_bo_cache ring_cache;
int closefd; /* call close(fd) upon destruction */
@@ -116,8 +115,7 @@
drm_private void fd_device_del_locked(struct fd_device *dev);
struct fd_pipe_funcs {
- struct fd_ringbuffer * (*ringbuffer_new)(struct fd_pipe *pipe, uint32_t size,
- enum fd_ringbuffer_flags flags);
+ struct fd_ringbuffer * (*ringbuffer_new)(struct fd_pipe *pipe, uint32_t size);
int (*get_param)(struct fd_pipe *pipe, enum fd_param_id param, uint64_t *value);
int (*wait)(struct fd_pipe *pipe, uint32_t timestamp, uint64_t timeout);
void (*destroy)(struct fd_pipe *pipe);
@@ -127,10 +125,14 @@
struct fd_device *dev;
enum fd_pipe_id id;
uint32_t gpu_id;
- atomic_t refcnt;
const struct fd_pipe_funcs *funcs;
};
+struct fd_ringmarker {
+ struct fd_ringbuffer *ring;
+ uint32_t *cur;
+};
+
struct fd_ringbuffer_funcs {
void * (*hostptr)(struct fd_ringbuffer *ring);
int (*flush)(struct fd_ringbuffer *ring, uint32_t *last_start,
@@ -140,7 +142,8 @@
void (*emit_reloc)(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc);
uint32_t (*emit_reloc_ring)(struct fd_ringbuffer *ring,
- struct fd_ringbuffer *target, uint32_t cmd_idx);
+ struct fd_ringbuffer *target, uint32_t cmd_idx,
+ uint32_t submit_offset, uint32_t size);
uint32_t (*cmd_count)(struct fd_ringbuffer *ring);
void (*destroy)(struct fd_ringbuffer *ring);
};
@@ -163,19 +166,11 @@
atomic_t refcnt;
const struct fd_bo_funcs *funcs;
- enum {
- NO_CACHE = 0,
- BO_CACHE = 1,
- RING_CACHE = 2,
- } bo_reuse;
-
+ int bo_reuse;
struct list_head list; /* bucket-list entry */
time_t free_time; /* time when added to bucket-list */
};
-drm_private struct fd_bo *fd_bo_new_ring(struct fd_device *dev,
- uint32_t size, uint32_t flags);
-
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
#define enable_debug 0 /* TODO make dynamic */
diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c
index 8f0093a..3834b51 100644
--- a/freedreno/freedreno_ringbuffer.c
+++ b/freedreno/freedreno_ringbuffer.c
@@ -32,24 +32,15 @@
#include "freedreno_priv.h"
#include "freedreno_ringbuffer.h"
-drm_public struct fd_ringbuffer *
-fd_ringbuffer_new_flags(struct fd_pipe *pipe, uint32_t size,
- enum fd_ringbuffer_flags flags)
+struct fd_ringbuffer *
+fd_ringbuffer_new(struct fd_pipe *pipe, uint32_t size)
{
struct fd_ringbuffer *ring;
- /* we can't really support "growable" rb's in general for
- * stateobj's since we need a single gpu addr (ie. can't
- * do the trick of a chain of IB packets):
- */
- if (flags & FD_RINGBUFFER_OBJECT)
- assert(size);
-
- ring = pipe->funcs->ringbuffer_new(pipe, size, flags);
+ ring = pipe->funcs->ringbuffer_new(pipe, size);
if (!ring)
return NULL;
- ring->flags = flags;
ring->pipe = pipe;
ring->start = ring->funcs->hostptr(ring);
ring->end = &(ring->start[ring->size/4]);
@@ -59,48 +50,23 @@
return ring;
}
-drm_public struct fd_ringbuffer *
-fd_ringbuffer_new(struct fd_pipe *pipe, uint32_t size)
+void fd_ringbuffer_del(struct fd_ringbuffer *ring)
{
- return fd_ringbuffer_new_flags(pipe, size, 0);
-}
-
-drm_public struct fd_ringbuffer *
-fd_ringbuffer_new_object(struct fd_pipe *pipe, uint32_t size)
-{
- return fd_ringbuffer_new_flags(pipe, size, FD_RINGBUFFER_OBJECT);
-}
-
-drm_public void fd_ringbuffer_del(struct fd_ringbuffer *ring)
-{
- if (!atomic_dec_and_test(&ring->refcnt))
- return;
-
fd_ringbuffer_reset(ring);
ring->funcs->destroy(ring);
}
-drm_public struct fd_ringbuffer *
-fd_ringbuffer_ref(struct fd_ringbuffer *ring)
-{
- STATIC_ASSERT(sizeof(ring->refcnt) <= sizeof(ring->__pad));
- atomic_inc(&ring->refcnt);
- return ring;
-}
-
/* ringbuffers which are IB targets should set the toplevel rb (ie.
* the IB source) as it's parent before emitting reloc's, to ensure
* the bookkeeping works out properly.
*/
-drm_public void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
+void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
struct fd_ringbuffer *parent)
{
- /* state objects should not be parented! */
- assert(!(ring->flags & FD_RINGBUFFER_OBJECT));
ring->parent = parent;
}
-drm_public void fd_ringbuffer_reset(struct fd_ringbuffer *ring)
+void fd_ringbuffer_reset(struct fd_ringbuffer *ring)
{
uint32_t *start = ring->start;
if (ring->pipe->id == FD_PIPE_2D)
@@ -110,18 +76,18 @@
ring->funcs->reset(ring);
}
-drm_public int fd_ringbuffer_flush(struct fd_ringbuffer *ring)
+int fd_ringbuffer_flush(struct fd_ringbuffer *ring)
{
return ring->funcs->flush(ring, ring->last_start, -1, NULL);
}
-drm_public int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd,
+int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd,
int *out_fence_fd)
{
return ring->funcs->flush(ring, ring->last_start, in_fence_fd, out_fence_fd);
}
-drm_public void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords)
+void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords)
{
assert(ring->funcs->grow); /* unsupported on kgsl */
@@ -137,46 +103,89 @@
ring->cur = ring->last_start = ring->start;
}
-drm_public uint32_t fd_ringbuffer_timestamp(struct fd_ringbuffer *ring)
+uint32_t fd_ringbuffer_timestamp(struct fd_ringbuffer *ring)
{
return ring->last_timestamp;
}
-drm_public void fd_ringbuffer_reloc(struct fd_ringbuffer *ring,
+void fd_ringbuffer_reloc(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc)
{
assert(ring->pipe->gpu_id < 500);
ring->funcs->emit_reloc(ring, reloc);
}
-drm_public void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring,
+void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring,
const struct fd_reloc *reloc)
{
ring->funcs->emit_reloc(ring, reloc);
}
-drm_public uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring)
+void fd_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
+ struct fd_ringmarker *target, struct fd_ringmarker *end)
+{
+ uint32_t submit_offset, size;
+
+ /* This function is deprecated and not supported on 64b devices: */
+ assert(ring->pipe->gpu_id < 500);
+ assert(target->ring == end->ring);
+
+ submit_offset = offset_bytes(target->cur, target->ring->start);
+ size = offset_bytes(end->cur, target->cur);
+
+ ring->funcs->emit_reloc_ring(ring, target->ring, 0, submit_offset, size);
+}
+
+uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring)
{
if (!ring->funcs->cmd_count)
return 1;
return ring->funcs->cmd_count(ring);
}
-drm_public uint32_t
+uint32_t
fd_ringbuffer_emit_reloc_ring_full(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx)
{
- return ring->funcs->emit_reloc_ring(ring, target, cmd_idx);
+ uint32_t size = offset_bytes(target->cur, target->start);
+ return ring->funcs->emit_reloc_ring(ring, target, cmd_idx, 0, size);
}
-drm_public uint32_t
-fd_ringbuffer_size(struct fd_ringbuffer *ring)
+struct fd_ringmarker * fd_ringmarker_new(struct fd_ringbuffer *ring)
{
- /* only really needed for stateobj ringbuffers, and won't really
- * do what you expect for growable rb's.. so lets just restrict
- * this to stateobj's for now:
- */
- assert(ring->flags & FD_RINGBUFFER_OBJECT);
- return offset_bytes(ring->cur, ring->start);
+ struct fd_ringmarker *marker = NULL;
+
+ marker = calloc(1, sizeof(*marker));
+ if (!marker) {
+ ERROR_MSG("allocation failed");
+ return NULL;
+ }
+
+ marker->ring = ring;
+
+ marker->cur = marker->ring->cur;
+
+ return marker;
}
+void fd_ringmarker_del(struct fd_ringmarker *marker)
+{
+ free(marker);
+}
+
+void fd_ringmarker_mark(struct fd_ringmarker *marker)
+{
+ marker->cur = marker->ring->cur;
+}
+
+uint32_t fd_ringmarker_dwords(struct fd_ringmarker *start,
+ struct fd_ringmarker *end)
+{
+ return end->cur - start->cur;
+}
+
+int fd_ringmarker_flush(struct fd_ringmarker *marker)
+{
+ struct fd_ringbuffer *ring = marker->ring;
+ return ring->funcs->flush(ring, marker->cur, -1, NULL);
+}
diff --git a/freedreno/freedreno_ringbuffer.h b/freedreno/freedreno_ringbuffer.h
index bc41a31..c501fba 100644
--- a/freedreno/freedreno_ringbuffer.h
+++ b/freedreno/freedreno_ringbuffer.h
@@ -33,33 +33,12 @@
/* the ringbuffer object is not opaque so that OUT_RING() type stuff
* can be inlined. Note that users should not make assumptions about
- * the size of this struct.
+ * the size of this struct.. more stuff will be added when we eventually
+ * have a kernel driver that can deal w/ reloc's..
*/
struct fd_ringbuffer_funcs;
-
-enum fd_ringbuffer_flags {
-
- /* Ringbuffer is a "state object", which is potentially reused
- * many times, rather than being used in one-shot mode linked
- * to a parent ringbuffer.
- */
- FD_RINGBUFFER_OBJECT = 0x1,
-
- /* Hint that the stateobj will be used for streaming state
- * that is used once or a few times and then discarded.
- *
- * For sub-allocation, non streaming stateobj's should be
- * sub-allocated from a page size buffer, so one long lived
- * state obj doesn't prevent other pages from being freed.
- * (Ie. it would be no worse than allocating a page sized
- * bo for each small non-streaming stateobj).
- *
- * But streaming stateobj's could be sub-allocated from a
- * larger buffer to reduce the alloc/del overhead.
- */
- FD_RINGBUFFER_STREAMING = 0x2,
-};
+struct fd_ringmarker;
struct fd_ringbuffer {
int size;
@@ -68,41 +47,13 @@
const struct fd_ringbuffer_funcs *funcs;
uint32_t last_timestamp;
struct fd_ringbuffer *parent;
-
- /* for users of fd_ringbuffer to store their own private per-
- * ringbuffer data
- */
- void *user;
-
- enum fd_ringbuffer_flags flags;
-
- /* This is a bit gross, but we can't use atomic_t in exported
- * headers. OTOH, we don't need the refcnt to be publicly
- * visible. The only reason that this struct is exported is
- * because fd_ringbuffer_emit needs to be something that can
- * be inlined for performance reasons.
- */
- union {
-#ifdef HAS_ATOMIC_OPS
- atomic_t refcnt;
-#endif
- uint64_t __pad;
- };
};
struct fd_ringbuffer * fd_ringbuffer_new(struct fd_pipe *pipe,
uint32_t size);
-will_be_deprecated
-struct fd_ringbuffer * fd_ringbuffer_new_object(struct fd_pipe *pipe,
- uint32_t size);
-struct fd_ringbuffer * fd_ringbuffer_new_flags(struct fd_pipe *pipe,
- uint32_t size, enum fd_ringbuffer_flags flags);
-
-struct fd_ringbuffer *fd_ringbuffer_ref(struct fd_ringbuffer *ring);
void fd_ringbuffer_del(struct fd_ringbuffer *ring);
void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring,
struct fd_ringbuffer *parent);
-will_be_deprecated
void fd_ringbuffer_reset(struct fd_ringbuffer *ring);
int fd_ringbuffer_flush(struct fd_ringbuffer *ring);
/* in_fence_fd: -1 for no in-fence, else fence fd
@@ -134,9 +85,17 @@
void fd_ringbuffer_reloc2(struct fd_ringbuffer *ring, const struct fd_reloc *reloc);
will_be_deprecated void fd_ringbuffer_reloc(struct fd_ringbuffer *ring, const struct fd_reloc *reloc);
+will_be_deprecated void fd_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
+ struct fd_ringmarker *target, struct fd_ringmarker *end);
uint32_t fd_ringbuffer_cmd_count(struct fd_ringbuffer *ring);
uint32_t fd_ringbuffer_emit_reloc_ring_full(struct fd_ringbuffer *ring,
struct fd_ringbuffer *target, uint32_t cmd_idx);
-uint32_t fd_ringbuffer_size(struct fd_ringbuffer *ring);
+
+will_be_deprecated struct fd_ringmarker * fd_ringmarker_new(struct fd_ringbuffer *ring);
+will_be_deprecated void fd_ringmarker_del(struct fd_ringmarker *marker);
+will_be_deprecated void fd_ringmarker_mark(struct fd_ringmarker *marker);
+will_be_deprecated uint32_t fd_ringmarker_dwords(struct fd_ringmarker *start,
+ struct fd_ringmarker *end);
+will_be_deprecated int fd_ringmarker_flush(struct fd_ringmarker *marker);
#endif /* FREEDRENO_RINGBUFFER_H_ */
diff --git a/freedreno/kgsl/README b/freedreno/kgsl/README
index c46ba08..56874b4 100644
--- a/freedreno/kgsl/README
+++ b/freedreno/kgsl/README
@@ -1,4 +1,4 @@
-This is a historical description of what is now the kgsl backend
+This is a historical discription of what is now the kgsl backend
in libdrm freedreno (before the upstream drm/msm driver). Note
that the kgsl backend requires the "kgsl-drm" shim driver, which
usually is in disrepair (QCOM does not build it for android), and
diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c
index 7a6af2f..c6d2d49 100644
--- a/freedreno/kgsl/kgsl_bo.c
+++ b/freedreno/kgsl/kgsl_bo.c
@@ -177,7 +177,7 @@
return bo;
}
-drm_public struct fd_bo *
+struct fd_bo *
fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size)
{
struct fd_bo *bo;
diff --git a/freedreno/kgsl/kgsl_priv.h b/freedreno/kgsl/kgsl_priv.h
index a6bf2d4..41b1392 100644
--- a/freedreno/kgsl/kgsl_priv.h
+++ b/freedreno/kgsl/kgsl_priv.h
@@ -106,7 +106,7 @@
enum fd_pipe_id id, uint32_t prio);
drm_private struct fd_ringbuffer * kgsl_ringbuffer_new(struct fd_pipe *pipe,
- uint32_t size, enum fd_ringbuffer_flags flags);
+ uint32_t size);
drm_private int kgsl_bo_new_handle(struct fd_device *dev,
uint32_t size, uint32_t flags, uint32_t *handle);
diff --git a/freedreno/kgsl/kgsl_ringbuffer.c b/freedreno/kgsl/kgsl_ringbuffer.c
index 9abf0ad..a756ded 100644
--- a/freedreno/kgsl/kgsl_ringbuffer.c
+++ b/freedreno/kgsl/kgsl_ringbuffer.c
@@ -28,7 +28,6 @@
#include <assert.h>
-#include "xf86atomic.h"
#include "freedreno_ringbuffer.h"
#include "kgsl_priv.h"
@@ -175,12 +174,13 @@
}
static uint32_t kgsl_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
- struct fd_ringbuffer *target, uint32_t cmd_idx)
+ struct fd_ringbuffer *target, uint32_t cmd_idx,
+ uint32_t submit_offset, uint32_t size)
{
struct kgsl_ringbuffer *target_ring = to_kgsl_ringbuffer(target);
assert(cmd_idx == 0);
- (*ring->cur++) = target_ring->bo->gpuaddr;
- return offset_bytes(target->cur, target->start);
+ (*ring->cur++) = target_ring->bo->gpuaddr + submit_offset;
+ return size;
}
static void kgsl_ringbuffer_destroy(struct fd_ringbuffer *ring)
@@ -202,13 +202,11 @@
};
drm_private struct fd_ringbuffer * kgsl_ringbuffer_new(struct fd_pipe *pipe,
- uint32_t size, enum fd_ringbuffer_flags flags)
+ uint32_t size)
{
struct kgsl_ringbuffer *kgsl_ring;
struct fd_ringbuffer *ring = NULL;
- assert(!flags);
-
kgsl_ring = calloc(1, sizeof(*kgsl_ring));
if (!kgsl_ring) {
ERROR_MSG("allocation failed");
@@ -216,8 +214,6 @@
}
ring = &kgsl_ring->base;
- atomic_set(&ring->refcnt, 1);
-
ring->funcs = &funcs;
ring->size = size;
diff --git a/freedreno/meson.build b/freedreno/meson.build
index c9aba06..015b7fb 100644
--- a/freedreno/meson.build
+++ b/freedreno/meson.build
@@ -42,7 +42,7 @@
libdrm_freedreno = shared_library(
'drm_freedreno',
[files_freedreno, config_file],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm],
dependencies : [dep_valgrind, dep_pthread_stubs, dep_rt, dep_atomic_ops],
link_with : libdrm,
diff --git a/freedreno/msm/msm_device.c b/freedreno/msm/msm_device.c
index 58b0746..7bb5767 100644
--- a/freedreno/msm/msm_device.c
+++ b/freedreno/msm/msm_device.c
@@ -35,6 +35,7 @@
static void msm_device_destroy(struct fd_device *dev)
{
struct msm_device *msm_dev = to_msm_device(dev);
+ fd_bo_cache_cleanup(&msm_dev->ring_cache, 0);
free(msm_dev);
}
@@ -57,6 +58,8 @@
dev = &msm_dev->base;
dev->funcs = &funcs;
+ fd_bo_cache_init(&msm_dev->ring_cache, TRUE);
+
dev->bo_size = sizeof(struct msm_bo);
return dev;
diff --git a/include/drm/msm_drm.h b/freedreno/msm/msm_drm.h
similarity index 98%
rename from include/drm/msm_drm.h
rename to freedreno/msm/msm_drm.h
index c06d0a5..dac49e5 100644
--- a/include/drm/msm_drm.h
+++ b/freedreno/msm/msm_drm.h
@@ -25,6 +25,7 @@
#ifndef __MSM_DRM_H__
#define __MSM_DRM_H__
+#include <stddef.h>
#include "drm.h"
#if defined(__cplusplus)
@@ -201,12 +202,10 @@
#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
-#define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
#define MSM_SUBMIT_FLAGS ( \
MSM_SUBMIT_NO_IMPLICIT | \
MSM_SUBMIT_FENCE_FD_IN | \
MSM_SUBMIT_FENCE_FD_OUT | \
- MSM_SUBMIT_SUDO | \
0)
/* Each cmdstream submit consists of a table of buffers involved, and
diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c
index e070b31..f28778e 100644
--- a/freedreno/msm/msm_pipe.c
+++ b/freedreno/msm/msm_pipe.c
@@ -138,12 +138,6 @@
{
struct msm_pipe *msm_pipe = to_msm_pipe(pipe);
close_submitqueue(pipe, msm_pipe->queue_id);
-
- if (msm_pipe->suballoc_ring) {
- fd_ringbuffer_del(msm_pipe->suballoc_ring);
- msm_pipe->suballoc_ring = NULL;
- }
-
free(msm_pipe);
}
diff --git a/freedreno/msm/msm_priv.h b/freedreno/msm/msm_priv.h
index cc951fb..88ac3aa 100644
--- a/freedreno/msm/msm_priv.h
+++ b/freedreno/msm/msm_priv.h
@@ -57,17 +57,6 @@
uint32_t gmem;
uint32_t chip_id;
uint32_t queue_id;
-
- /* Allow for sub-allocation of stateobj ring buffers (ie. sharing
- * the same underlying bo)..
- *
- * This takes advantage of each context having it's own fd_pipe,
- * so we don't have to worry about access from multiple threads.
- *
- * We also rely on previous stateobj having been fully constructed
- * so we can reclaim extra space at it's end.
- */
- struct fd_ringbuffer *suballoc_ring;
};
static inline struct msm_pipe * to_msm_pipe(struct fd_pipe *x)
@@ -79,7 +68,7 @@
enum fd_pipe_id id, uint32_t prio);
drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe,
- uint32_t size, enum fd_ringbuffer_flags flags);
+ uint32_t size);
struct msm_bo {
struct fd_bo base;
@@ -112,30 +101,4 @@
tv->tv_nsec = t.tv_nsec + ns - (s * 1000000000);
}
-/*
- * Stupid/simple growable array implementation:
- */
-
-static inline void *
-grow(void *ptr, uint32_t nr, uint32_t *max, uint32_t sz)
-{
- if ((nr + 1) > *max) {
- if ((*max * 2) < (nr + 1))
- *max = nr + 5;
- else
- *max = *max * 2;
- ptr = realloc(ptr, *max * sz);
- }
- return ptr;
-}
-
-#define DECLARE_ARRAY(type, name) \
- unsigned nr_ ## name, max_ ## name; \
- type * name;
-
-#define APPEND(x, name) ({ \
- (x)->name = grow((x)->name, (x)->nr_ ## name, &(x)->max_ ## name, sizeof((x)->name[0])); \
- (x)->nr_ ## name ++; \
-})
-
#endif /* MSM_PRIV_H_ */
diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c
index 7b9df4a..a87e1b9 100644
--- a/freedreno/msm/msm_ringbuffer.c
+++ b/freedreno/msm/msm_ringbuffer.c
@@ -29,7 +29,6 @@
#include <assert.h>
#include <inttypes.h>
-#include "xf86atomic.h"
#include "freedreno_ringbuffer.h"
#include "msm_priv.h"
@@ -43,12 +42,10 @@
struct fd_bo *ring_bo;
/* reloc's table: */
- DECLARE_ARRAY(struct drm_msm_gem_submit_reloc, relocs);
+ struct drm_msm_gem_submit_reloc *relocs;
+ uint32_t nr_relocs, max_relocs;
uint32_t size;
-
- /* has cmd already been added to parent rb's submit.cmds table? */
- int is_appended_to_submit;
};
struct msm_ringbuffer {
@@ -61,20 +58,24 @@
*/
struct {
/* bo's table: */
- DECLARE_ARRAY(struct drm_msm_gem_submit_bo, bos);
+ struct drm_msm_gem_submit_bo *bos;
+ uint32_t nr_bos, max_bos;
/* cmd's table: */
- DECLARE_ARRAY(struct drm_msm_gem_submit_cmd, cmds);
+ struct drm_msm_gem_submit_cmd *cmds;
+ uint32_t nr_cmds, max_cmds;
} submit;
/* should have matching entries in submit.bos: */
/* Note, only in parent ringbuffer */
- DECLARE_ARRAY(struct fd_bo *, bos);
+ struct fd_bo **bos;
+ uint32_t nr_bos, max_bos;
/* should have matching entries in submit.cmds: */
- DECLARE_ARRAY(struct msm_cmd *, cmds);
+ struct msm_cmd **cmds;
+ uint32_t nr_cmds, max_cmds;
- /* List of physical cmdstream buffers (msm_cmd) associated with this
+ /* List of physical cmdstream buffers (msm_cmd) assocated with this
* logical fd_ringbuffer.
*
* Note that this is different from msm_ringbuffer::cmds (which
@@ -88,24 +89,10 @@
int is_growable;
unsigned cmd_count;
- unsigned offset; /* for sub-allocated stateobj rb's */
-
unsigned seqno;
/* maps fd_bo to idx: */
void *bo_table;
-
- /* maps msm_cmd to drm_msm_gem_submit_cmd in parent rb. Each rb has a
- * list of msm_cmd's which correspond to each chunk of cmdstream in
- * a 'growable' rb. For each of those we need to create one
- * drm_msm_gem_submit_cmd in the parent rb which collects the state
- * for the submit ioctl. Because we can have multiple IB's to the same
- * target rb (for example, or same stateobj emit multiple times), and
- * because in theory we can have multiple different rb's that have a
- * reference to a given target, we need a hashtable to track this per
- * rb.
- */
- void *cmd_table;
};
static inline struct msm_ringbuffer * to_msm_ringbuffer(struct fd_ringbuffer *x)
@@ -116,25 +103,51 @@
#define INIT_SIZE 0x1000
static pthread_mutex_t idx_lock = PTHREAD_MUTEX_INITIALIZER;
+drm_private extern pthread_mutex_t table_lock;
-static struct msm_cmd *current_cmd(struct fd_ringbuffer *ring)
+static void ring_bo_del(struct fd_device *dev, struct fd_bo *bo)
{
- struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
- assert(!LIST_IS_EMPTY(&msm_ring->cmd_list));
- return LIST_LAST_ENTRY(&msm_ring->cmd_list, struct msm_cmd, list);
+ int ret;
+
+ pthread_mutex_lock(&table_lock);
+ ret = fd_bo_cache_free(&to_msm_device(dev)->ring_cache, bo);
+ pthread_mutex_unlock(&table_lock);
+
+ if (ret == 0)
+ return;
+
+ fd_bo_del(bo);
+}
+
+static struct fd_bo * ring_bo_new(struct fd_device *dev, uint32_t size)
+{
+ struct fd_bo *bo;
+
+ bo = fd_bo_cache_alloc(&to_msm_device(dev)->ring_cache, &size, 0);
+ if (bo)
+ return bo;
+
+ bo = fd_bo_new(dev, size, 0);
+ if (!bo)
+ return NULL;
+
+ /* keep ringbuffer bo's out of the normal bo cache: */
+ bo->bo_reuse = FALSE;
+
+ return bo;
}
static void ring_cmd_del(struct msm_cmd *cmd)
{
- fd_bo_del(cmd->ring_bo);
+ if (cmd->ring_bo)
+ ring_bo_del(cmd->ring->pipe->dev, cmd->ring_bo);
list_del(&cmd->list);
to_msm_ringbuffer(cmd->ring)->cmd_count--;
free(cmd->relocs);
free(cmd);
}
-static struct msm_cmd * ring_cmd_new(struct fd_ringbuffer *ring, uint32_t size,
- enum fd_ringbuffer_flags flags)
+static struct msm_cmd * ring_cmd_new(struct fd_ringbuffer *ring, uint32_t size)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
struct msm_cmd *cmd = calloc(1, sizeof(*cmd));
@@ -143,48 +156,7 @@
return NULL;
cmd->ring = ring;
-
- /* TODO separate suballoc buffer for small non-streaming state, using
- * smaller page-sized backing bo's.
- */
- if (flags & FD_RINGBUFFER_STREAMING) {
- struct msm_pipe *msm_pipe = to_msm_pipe(ring->pipe);
- unsigned suballoc_offset = 0;
- struct fd_bo *suballoc_bo = NULL;
-
- if (msm_pipe->suballoc_ring) {
- struct msm_ringbuffer *suballoc_ring = to_msm_ringbuffer(msm_pipe->suballoc_ring);
-
- assert(msm_pipe->suballoc_ring->flags & FD_RINGBUFFER_OBJECT);
- assert(suballoc_ring->cmd_count == 1);
-
- suballoc_bo = current_cmd(msm_pipe->suballoc_ring)->ring_bo;
-
- suballoc_offset = fd_ringbuffer_size(msm_pipe->suballoc_ring) +
- suballoc_ring->offset;
-
- suballoc_offset = ALIGN(suballoc_offset, 0x10);
-
- if ((size + suballoc_offset) > suballoc_bo->size) {
- suballoc_bo = NULL;
- }
- }
-
- if (!suballoc_bo) {
- cmd->ring_bo = fd_bo_new_ring(ring->pipe->dev, 0x8000, 0);
- msm_ring->offset = 0;
- } else {
- cmd->ring_bo = fd_bo_ref(suballoc_bo);
- msm_ring->offset = suballoc_offset;
- }
-
- if (msm_pipe->suballoc_ring)
- fd_ringbuffer_del(msm_pipe->suballoc_ring);
-
- msm_pipe->suballoc_ring = fd_ringbuffer_ref(ring);
- } else {
- cmd->ring_bo = fd_bo_new_ring(ring->pipe->dev, size, 0);
- }
+ cmd->ring_bo = ring_bo_new(ring->pipe->dev, size);
if (!cmd->ring_bo)
goto fail;
@@ -198,6 +170,30 @@
return NULL;
}
+static void *grow(void *ptr, uint32_t nr, uint32_t *max, uint32_t sz)
+{
+ if ((nr + 1) > *max) {
+ if ((*max * 2) < (nr + 1))
+ *max = nr + 5;
+ else
+ *max = *max * 2;
+ ptr = realloc(ptr, *max * sz);
+ }
+ return ptr;
+}
+
+#define APPEND(x, name) ({ \
+ (x)->name = grow((x)->name, (x)->nr_ ## name, &(x)->max_ ## name, sizeof((x)->name[0])); \
+ (x)->nr_ ## name ++; \
+})
+
+static struct msm_cmd *current_cmd(struct fd_ringbuffer *ring)
+{
+ struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
+ assert(!LIST_IS_EMPTY(&msm_ring->cmd_list));
+ return LIST_LAST_ENTRY(&msm_ring->cmd_list, struct msm_cmd, list);
+}
+
static uint32_t append_bo(struct fd_ringbuffer *ring, struct fd_bo *bo)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
@@ -249,43 +245,31 @@
return idx;
}
+static int check_cmd_bo(struct fd_ringbuffer *ring,
+ struct drm_msm_gem_submit_cmd *cmd, struct fd_bo *bo)
+{
+ struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
+ return msm_ring->submit.bos[cmd->submit_idx].handle == bo->handle;
+}
+
/* Ensure that submit has corresponding entry in cmds table for the
* target cmdstream buffer:
- *
- * Returns TRUE if new cmd added (else FALSE if it was already in
- * the cmds table)
*/
-static int get_cmd(struct fd_ringbuffer *ring, struct msm_cmd *target_cmd,
+static void get_cmd(struct fd_ringbuffer *ring, struct msm_cmd *target_cmd,
uint32_t submit_offset, uint32_t size, uint32_t type)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
struct drm_msm_gem_submit_cmd *cmd;
uint32_t i;
- void *val;
- if (!msm_ring->cmd_table)
- msm_ring->cmd_table = drmHashCreate();
-
- /* figure out if we already have a cmd buf.. short-circuit hash
- * lookup if:
- * - target cmd has never been added to submit.cmds
- * - target cmd is not a streaming stateobj (which unlike longer
- * lived CSO stateobj, is not expected to be reused with multiple
- * submits)
- */
- if (target_cmd->is_appended_to_submit &&
- !(target_cmd->ring->flags & FD_RINGBUFFER_STREAMING) &&
- !drmHashLookup(msm_ring->cmd_table, (unsigned long)target_cmd, &val)) {
- i = VOID2U64(val);
+ /* figure out if we already have a cmd buf: */
+ for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
cmd = &msm_ring->submit.cmds[i];
-
- assert(cmd->submit_offset == submit_offset);
- assert(cmd->size == size);
- assert(cmd->type == type);
- assert(msm_ring->submit.bos[cmd->submit_idx].handle ==
- target_cmd->ring_bo->handle);
-
- return FALSE;
+ if ((cmd->submit_offset == submit_offset) &&
+ (cmd->size == size) &&
+ (cmd->type == type) &&
+ check_cmd_bo(ring, cmd, target_cmd->ring_bo))
+ return;
}
/* create cmd buf if not: */
@@ -299,23 +283,27 @@
cmd->size = size;
cmd->pad = 0;
- target_cmd->is_appended_to_submit = TRUE;
-
- if (!(target_cmd->ring->flags & FD_RINGBUFFER_STREAMING)) {
- drmHashInsert(msm_ring->cmd_table, (unsigned long)target_cmd,
- U642VOID(i));
- }
-
target_cmd->size = size;
-
- return TRUE;
}
static void * msm_ringbuffer_hostptr(struct fd_ringbuffer *ring)
{
- struct msm_cmd *cmd = current_cmd(ring);
- uint8_t *base = fd_bo_map(cmd->ring_bo);
- return base + to_msm_ringbuffer(ring)->offset;
+ return fd_bo_map(current_cmd(ring)->ring_bo);
+}
+
+static uint32_t find_next_reloc_idx(struct msm_cmd *msm_cmd,
+ uint32_t start, uint32_t offset)
+{
+ uint32_t i;
+
+ /* a binary search would be more clever.. */
+ for (i = start; i < msm_cmd->nr_relocs; i++) {
+ struct drm_msm_gem_submit_reloc *reloc = &msm_cmd->relocs[i];
+ if (reloc->submit_offset >= offset)
+ return i;
+ }
+
+ return i;
}
static void delete_cmds(struct msm_ringbuffer *msm_ring)
@@ -334,20 +322,14 @@
for (i = 0; i < msm_ring->nr_bos; i++) {
struct msm_bo *msm_bo = to_msm_bo(msm_ring->bos[i]);
- if (!msm_bo)
- continue;
msm_bo->current_ring_seqno = 0;
fd_bo_del(&msm_bo->base);
}
- for (i = 0; i < msm_ring->nr_cmds; i++) {
- struct msm_cmd *msm_cmd = msm_ring->cmds[i];
-
- if (msm_cmd->ring == ring)
- continue;
-
- if (msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT)
- fd_ringbuffer_del(msm_cmd->ring);
+ /* for each of the cmd buffers, clear their reloc's: */
+ for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
+ struct msm_cmd *target_cmd = msm_ring->cmds[i];
+ target_cmd->nr_relocs = 0;
}
msm_ring->submit.nr_cmds = 0;
@@ -360,11 +342,6 @@
msm_ring->bo_table = NULL;
}
- if (msm_ring->cmd_table) {
- drmHashDestroy(msm_ring->cmd_table);
- msm_ring->cmd_table = NULL;
- }
-
if (msm_ring->is_growable) {
delete_cmds(msm_ring);
} else {
@@ -414,63 +391,17 @@
}
}
-static struct drm_msm_gem_submit_reloc *
-handle_stateobj_relocs(struct fd_ringbuffer *parent, struct fd_ringbuffer *stateobj,
- struct drm_msm_gem_submit_reloc *orig_relocs, unsigned nr_relocs)
-{
- struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(stateobj);
- struct drm_msm_gem_submit_reloc *relocs = malloc(nr_relocs * sizeof(*relocs));
- unsigned i;
-
- for (i = 0; i < nr_relocs; i++) {
- unsigned idx = orig_relocs[i].reloc_idx;
- struct fd_bo *bo = msm_ring->bos[idx];
- unsigned flags = 0;
-
- if (msm_ring->submit.bos[idx].flags & MSM_SUBMIT_BO_READ)
- flags |= FD_RELOC_READ;
- if (msm_ring->submit.bos[idx].flags & MSM_SUBMIT_BO_WRITE)
- flags |= FD_RELOC_WRITE;
-
- relocs[i] = orig_relocs[i];
- relocs[i].reloc_idx = bo2idx(parent, bo, flags);
- }
-
- /* stateobj rb's could have reloc's to other stateobj rb's which didn't
- * get propagated to the parent rb at _emit_reloc_ring() time (because
- * the parent wasn't known then), so fix that up now:
- */
- for (i = 0; i < msm_ring->nr_cmds; i++) {
- struct msm_cmd *msm_cmd = msm_ring->cmds[i];
- struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
-
- if (msm_ring->cmds[i]->ring == stateobj)
- continue;
-
- assert(msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT);
-
- if (get_cmd(parent, msm_cmd, cmd->submit_offset, cmd->size, cmd->type)) {
- fd_ringbuffer_ref(msm_cmd->ring);
- }
- }
-
- return relocs;
-}
-
static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start,
int in_fence_fd, int *out_fence_fd)
{
struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring);
- struct msm_pipe *msm_pipe = to_msm_pipe(ring->pipe);
struct drm_msm_gem_submit req = {
- .flags = msm_pipe->pipe,
- .queueid = msm_pipe->queue_id,
+ .flags = to_msm_pipe(ring->pipe)->pipe,
+ .queueid = to_msm_pipe(ring->pipe)->queue_id,
};
uint32_t i;
int ret;
- assert(!ring->parent);
-
if (in_fence_fd != -1) {
req.flags |= MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_NO_IMPLICIT;
req.fence_fd = in_fence_fd;
@@ -482,35 +413,22 @@
finalize_current_cmd(ring, last_start);
- /* for each of the cmd's fix up their reloc's: */
- for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
- struct msm_cmd *msm_cmd = msm_ring->cmds[i];
- struct drm_msm_gem_submit_reloc *relocs = msm_cmd->relocs;
- struct drm_msm_gem_submit_cmd *cmd;
- unsigned nr_relocs = msm_cmd->nr_relocs;
-
- /* for reusable stateobjs, the reloc table has reloc_idx that
- * points into it's own private bos table, rather than the global
- * bos table used for the submit, so we need to add the stateobj's
- * bos to the global table and construct new relocs table with
- * corresponding reloc_idx
- */
- if (msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT) {
- relocs = handle_stateobj_relocs(ring, msm_cmd->ring,
- relocs, nr_relocs);
- }
-
- cmd = &msm_ring->submit.cmds[i];
- cmd->relocs = VOID2U64(relocs);
- cmd->nr_relocs = nr_relocs;
- }
-
/* needs to be after get_cmd() as that could create bos/cmds table: */
req.bos = VOID2U64(msm_ring->submit.bos),
req.nr_bos = msm_ring->submit.nr_bos;
req.cmds = VOID2U64(msm_ring->submit.cmds),
req.nr_cmds = msm_ring->submit.nr_cmds;
+ /* for each of the cmd's fix up their reloc's: */
+ for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
+ struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
+ struct msm_cmd *msm_cmd = msm_ring->cmds[i];
+ uint32_t a = find_next_reloc_idx(msm_cmd, 0, cmd->submit_offset);
+ uint32_t b = find_next_reloc_idx(msm_cmd, a, cmd->submit_offset + cmd->size);
+ cmd->relocs = VOID2U64(&msm_cmd->relocs[a]);
+ cmd->nr_relocs = (b > a) ? b - a : 0;
+ }
+
DEBUG_MSG("nr_cmds=%u, nr_bos=%u", req.nr_cmds, req.nr_bos);
ret = drmCommandWriteRead(ring->pipe->dev->fd, DRM_MSM_GEM_SUBMIT,
@@ -530,15 +448,6 @@
}
}
- /* free dynamically constructed stateobj relocs tables: */
- for (i = 0; i < msm_ring->submit.nr_cmds; i++) {
- struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i];
- struct msm_cmd *msm_cmd = msm_ring->cmds[i];
- if (msm_cmd->ring->flags & FD_RINGBUFFER_OBJECT) {
- free(U642VOID(cmd->relocs));
- }
- }
-
flush_reset(ring);
return ret;
@@ -548,7 +457,7 @@
{
assert(to_msm_ringbuffer(ring)->is_growable);
finalize_current_cmd(ring, ring->last_start);
- ring_cmd_new(ring, size, 0);
+ ring_cmd_new(ring, size);
}
static void msm_ringbuffer_reset(struct fd_ringbuffer *ring)
@@ -572,8 +481,7 @@
reloc->reloc_offset = r->offset;
reloc->or = r->or;
reloc->shift = r->shift;
- reloc->submit_offset = offset_bytes(ring->cur, ring->start) +
- to_msm_ringbuffer(ring)->offset;
+ reloc->submit_offset = offset_bytes(ring->cur, ring->start);
addr = msm_bo->presumed;
if (reloc->shift < 0)
@@ -598,8 +506,7 @@
reloc_hi->reloc_offset = r->offset;
reloc_hi->or = r->orhi;
reloc_hi->shift = r->shift - 32;
- reloc_hi->submit_offset = offset_bytes(ring->cur, ring->start) +
- to_msm_ringbuffer(ring)->offset;
+ reloc_hi->submit_offset = offset_bytes(ring->cur, ring->start);
addr = msm_bo->presumed >> 32;
if (reloc_hi->shift < 0)
@@ -611,16 +518,13 @@
}
static uint32_t msm_ringbuffer_emit_reloc_ring(struct fd_ringbuffer *ring,
- struct fd_ringbuffer *target, uint32_t cmd_idx)
+ struct fd_ringbuffer *target, uint32_t cmd_idx,
+ uint32_t submit_offset, uint32_t size)
{
struct msm_cmd *cmd = NULL;
- struct msm_ringbuffer *msm_target = to_msm_ringbuffer(target);
uint32_t idx = 0;
- int added_cmd = FALSE;
- uint32_t size;
- uint32_t submit_offset = msm_target->offset;
- LIST_FOR_EACH_ENTRY(cmd, &msm_target->cmd_list, list) {
+ LIST_FOR_EACH_ENTRY(cmd, &to_msm_ringbuffer(target)->cmd_list, list) {
if (idx == cmd_idx)
break;
idx++;
@@ -628,7 +532,7 @@
assert(cmd && (idx == cmd_idx));
- if (idx < (msm_target->cmd_count - 1)) {
+ if (idx < (to_msm_ringbuffer(target)->cmd_count - 1)) {
/* All but the last cmd buffer is fully "baked" (ie. already has
* done get_cmd() to add it to the cmds table). But in this case,
* the size we get is invalid (since it is calculated from the
@@ -636,10 +540,7 @@
*/
size = cmd->size;
} else {
- struct fd_ringbuffer *parent = ring->parent ? ring->parent : ring;
- size = offset_bytes(target->cur, target->start);
- added_cmd = get_cmd(parent, cmd, submit_offset, size,
- MSM_SUBMIT_CMD_IB_TARGET_BUF);
+ get_cmd(ring, cmd, submit_offset, size, MSM_SUBMIT_CMD_IB_TARGET_BUF);
}
msm_ringbuffer_emit_reloc(ring, &(struct fd_reloc){
@@ -648,14 +549,6 @@
.offset = submit_offset,
});
- /* Unlike traditional ringbuffers which are deleted as a set (after
- * being flushed), mesa can't really guarantee that a stateobj isn't
- * destroyed after emitted but before flush, so we must hold a ref:
- */
- if (added_cmd && (target->flags & FD_RINGBUFFER_OBJECT)) {
- fd_ringbuffer_ref(target);
- }
-
return size;
}
@@ -690,7 +583,7 @@
};
drm_private struct fd_ringbuffer * msm_ringbuffer_new(struct fd_pipe *pipe,
- uint32_t size, enum fd_ringbuffer_flags flags)
+ uint32_t size)
{
struct msm_ringbuffer *msm_ring;
struct fd_ringbuffer *ring;
@@ -711,13 +604,11 @@
msm_ring->seqno = ++to_msm_device(pipe->dev)->ring_cnt;
ring = &msm_ring->base;
- atomic_set(&ring->refcnt, 1);
-
ring->funcs = &funcs;
ring->size = size;
ring->pipe = pipe; /* needed in ring_cmd_new() */
- ring_cmd_new(ring, size, flags);
+ ring_cmd_new(ring, size);
return ring;
}
diff --git a/include/drm/README b/include/drm/README
index ea2320c..b4658dd 100644
--- a/include/drm/README
+++ b/include/drm/README
@@ -71,7 +71,7 @@
In order to update the files do the following:
- Switch to a Linux kernel tree/branch which is not rebased.
- For example: drm-next (https://cgit.freedesktop.org/drm/drm)
+For example: airlied/drm-next
- Install the headers via `make headers_install' to a separate location.
- Copy the drm header[s] + git add + git commit.
- Note: Your commit message must include:
@@ -122,6 +122,11 @@
- License mismatch, missing DRM_IOCTL_OMAP_GEM_NEW and related struct
Status: ?
+msm_drm.h (located in $TOP/freedreno/msm/)
+ - License mismatch, missing MSM_PIPE_*, MSM_SUBMIT_*. Renamed
+drm_msm_gem_submit::flags, missing drm_msm_gem_submit::fence_fd.
+Status: ?
+
exynos_drm.h (living in $TOP/exynos)
- License mismatch, now using fixed size ints (but not everywhere). Lots of
new stuff.
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 015bd9f..c363b67 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -72,41 +72,12 @@
#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
-/**
- * DOC: memory domains
- *
- * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
- * Memory in this pool could be swapped out to disk if there is pressure.
- *
- * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
- * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
- * pages of system memory, allows GPU access system memory in a linezrized
- * fashion.
- *
- * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
- * carved out by the BIOS.
- *
- * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
- * across shader threads.
- *
- * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
- * execution of all the waves on a device.
- *
- * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
- * for appending data.
- */
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
#define AMDGPU_GEM_DOMAIN_GDS 0x8
#define AMDGPU_GEM_DOMAIN_GWS 0x10
#define AMDGPU_GEM_DOMAIN_OA 0x20
-#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
- AMDGPU_GEM_DOMAIN_GTT | \
- AMDGPU_GEM_DOMAIN_VRAM | \
- AMDGPU_GEM_DOMAIN_GDS | \
- AMDGPU_GEM_DOMAIN_GWS | \
- AMDGPU_GEM_DOMAIN_OA)
/* Flag that CPU access will be required for the case of VRAM domain */
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -124,10 +95,6 @@
#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
/* Flag that BO sharing will be explicitly synchronized */
#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
-/* Flag that indicates allocating MQD gart on GFX9, where the mtype
- * for the second page onward should be set to NC.
- */
-#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -204,15 +171,12 @@
/* unknown cause */
#define AMDGPU_CTX_UNKNOWN_RESET 3
-/* indicate gpu reset occurred after ctx created */
+/* indicate gpu reset occured after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
-/* indicate vram lost occurred after ctx created */
+/* indicate vram lost occured after ctx created */
#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
/* indicate some job from this context once cause gpu hang */
#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
-/* indicate some errors are detected by RAS */
-#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
-#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
/* Context priority level */
#define AMDGPU_CTX_PRIORITY_UNSET -2048
@@ -275,14 +239,13 @@
/* sched ioctl */
#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
-#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
struct drm_amdgpu_sched_in {
/* AMDGPU_SCHED_OP_* */
__u32 op;
__u32 fd;
__s32 priority;
- __u32 ctx_id;
+ __u32 flags;
};
union drm_amdgpu_sched {
@@ -330,12 +293,6 @@
/* GFX9 and later: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
-#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
-#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
-#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
-#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
-#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
-#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
@@ -516,8 +473,7 @@
#define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6
#define AMDGPU_HW_IP_VCN_ENC 7
-#define AMDGPU_HW_IP_VCN_JPEG 8
-#define AMDGPU_HW_IP_NUM 9
+#define AMDGPU_HW_IP_NUM 8
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
@@ -526,10 +482,6 @@
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
-#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
-#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
-#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
-#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
struct drm_amdgpu_cs_chunk {
__u32 chunk_id;
@@ -568,15 +520,6 @@
/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
-/* The IB fence should do the L2 writeback but not invalidate any shader
- * caches (L2/vL1/sL1/I$). */
-#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
-
-/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
- * This will reset wave ID counters for the IB.
- */
-#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
-
struct drm_amdgpu_cs_chunk_ib {
__u32 _pad;
/** AMDGPU_IB_FLAG_* */
@@ -610,13 +553,6 @@
__u32 handle;
};
-struct drm_amdgpu_cs_chunk_syncobj {
- __u32 handle;
- __u32 flags;
- __u64 point;
-};
-
-
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
@@ -684,15 +620,6 @@
#define AMDGPU_INFO_FW_ASD 0x0d
/* Subquery id: Query VCN firmware version */
#define AMDGPU_INFO_FW_VCN 0x0e
- /* Subquery id: Query GFX RLC SRLC firmware version */
- #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
- /* Subquery id: Query GFX RLC SRLG firmware version */
- #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
- /* Subquery id: Query GFX RLC SRLS firmware version */
- #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
- /* Subquery id: Query DMCU firmware version */
- #define AMDGPU_INFO_FW_DMCU 0x12
- #define AMDGPU_INFO_FW_TA 0x13
/* number of bytes moved for TTM migration */
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
/* the used VRAM size */
@@ -746,37 +673,6 @@
/* Number of VRAM page faults on CPU access. */
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
-/* query ras mask of enabled features*/
-#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
-
-/* RAS MASK: UMC (VRAM) */
-#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
-/* RAS MASK: SDMA */
-#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
-/* RAS MASK: GFX */
-#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
-/* RAS MASK: MMHUB */
-#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
-/* RAS MASK: ATHUB */
-#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
-/* RAS MASK: PCIE */
-#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
-/* RAS MASK: HDP */
-#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
-/* RAS MASK: XGMI */
-#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
-/* RAS MASK: DF */
-#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
-/* RAS MASK: SMN */
-#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
-/* RAS MASK: SEM */
-#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
-/* RAS MASK: MP0 */
-#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
-/* RAS MASK: MP1 */
-#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
-/* RAS MASK: FUSE */
-#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -913,7 +809,6 @@
#define AMDGPU_VRAM_TYPE_HBM 6
#define AMDGPU_VRAM_TYPE_DDR3 7
#define AMDGPU_VRAM_TYPE_DDR4 8
-#define AMDGPU_VRAM_TYPE_GDDR6 9
struct drm_amdgpu_info_device {
/** PCI Device ID */
@@ -993,8 +888,6 @@
__u64 high_va_offset;
/** The maximum high virtual address */
__u64 high_va_max;
- /* gfx10 pa_sc_tile_steering_override */
- __u32 pa_sc_tile_steering_override;
};
struct drm_amdgpu_info_hw_ip {
@@ -1048,7 +941,6 @@
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
-#define AMDGPU_FAMILY_NV 143 /* Navi10 */
#if defined(__cplusplus)
}
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 438abde..f0bd91d 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -44,7 +44,6 @@
#else /* One of the BSDs */
-#include <stdint.h>
#include <sys/ioccom.h>
#include <sys/types.h>
typedef int8_t __s8;
@@ -644,7 +643,6 @@
#define DRM_CAP_PAGE_FLIP_TARGET 0x11
#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
#define DRM_CAP_SYNCOBJ 0x13
-#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
/** DRM_IOCTL_GET_CAP ioctl argument type */
struct drm_get_cap {
@@ -676,22 +674,6 @@
*/
#define DRM_CLIENT_CAP_ATOMIC 3
-/**
- * DRM_CLIENT_CAP_ASPECT_RATIO
- *
- * If set to 1, the DRM core will provide aspect ratio information in modes.
- */
-#define DRM_CLIENT_CAP_ASPECT_RATIO 4
-
-/**
- * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
- *
- * If set to 1, the DRM core will expose special connectors to be used for
- * writing back to memory the scene setup in the commit. Depends on client
- * also supporting DRM_CLIENT_CAP_ATOMIC
- */
-#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
-
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
struct drm_set_client_cap {
__u64 capability;
@@ -731,18 +713,8 @@
__u32 pad;
};
-struct drm_syncobj_transfer {
- __u32 src_handle;
- __u32 dst_handle;
- __u64 src_point;
- __u64 dst_point;
- __u32 flags;
- __u32 pad;
-};
-
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
-#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
struct drm_syncobj_wait {
__u64 handles;
/* absolute timeout */
@@ -753,33 +725,12 @@
__u32 pad;
};
-struct drm_syncobj_timeline_wait {
- __u64 handles;
- /* wait on specific timeline point for every handles*/
- __u64 points;
- /* absolute timeout */
- __s64 timeout_nsec;
- __u32 count_handles;
- __u32 flags;
- __u32 first_signaled; /* only valid when not waiting all */
- __u32 pad;
-};
-
-
struct drm_syncobj_array {
__u64 handles;
__u32 count_handles;
__u32 pad;
};
-struct drm_syncobj_timeline_array {
- __u64 handles;
- __u64 points;
- __u32 count_handles;
- __u32 pad;
-};
-
-
/* Query current scanout sequence number */
struct drm_crtc_get_sequence {
__u32 crtc_id; /* requested crtc_id */
@@ -936,11 +887,6 @@
#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
-#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
-#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
-#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
-#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
-
/**
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x9f.
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
index 5c69090..e04613d 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/drm/drm_fourcc.h
@@ -30,50 +30,11 @@
extern "C" {
#endif
-/**
- * DOC: overview
- *
- * In the DRM subsystem, framebuffer pixel formats are described using the
- * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
- * fourcc code, a Format Modifier may optionally be provided, in order to
- * further describe the buffer's format - for example tiling or compression.
- *
- * Format Modifiers
- * ----------------
- *
- * Format modifiers are used in conjunction with a fourcc code, forming a
- * unique fourcc:modifier pair. This format:modifier pair must fully define the
- * format and data layout of the buffer, and should be the only way to describe
- * that particular buffer.
- *
- * Having multiple fourcc:modifier pairs which describe the same layout should
- * be avoided, as such aliases run the risk of different drivers exposing
- * different names for the same data format, forcing userspace to understand
- * that they are aliases.
- *
- * Format modifiers may change any property of the buffer, including the number
- * of planes and/or the required allocation size. Format modifiers are
- * vendor-namespaced, and as such the relationship between a fourcc code and a
- * modifier is specific to the modifer being used. For example, some modifiers
- * may preserve meaning - such as number of planes - from the fourcc code,
- * whereas others may not.
- *
- * Vendors should document their modifier usage in as much detail as
- * possible, to ensure maximum compatibility across devices, drivers and
- * applications.
- *
- * The authoritative list of format modifier codes is found in
- * `include/uapi/drm/drm_fourcc.h`
- */
-
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
((__u32)(c) << 16) | ((__u32)(d) << 24))
#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
-/* Reserve 0 for the invalid format specifier */
-#define DRM_FORMAT_INVALID 0
-
/* color index */
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
@@ -144,17 +105,6 @@
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
-/*
- * Floating point 64bpp RGB
- * IEEE 754-2008 binary16 half-precision float
- * [15:0] sign:exponent:mantissa 1:5:10
- */
-#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
-#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
-
-#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
-#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
-
/* packed YCbCr */
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
@@ -162,52 +112,6 @@
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
-#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
-
-/*
- * packed Y2xx indicate for each component, xx valid data occupy msb
- * 16-xx padding occupy lsb
- */
-#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
-#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
-#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
-
-/*
- * packed Y4xx indicate for each component, xx valid data occupy msb
- * 16-xx padding occupy lsb except Y410
- */
-#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
-#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
-
-#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
-#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
-#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
-
-/*
- * packed YCbCr420 2x2 tiled formats
- * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
- */
-/* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
-#define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
-/* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
-#define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
-
-/* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
-#define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
-/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
-#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
-
-/*
- * 1-plane YUV 4:2:0
- * In these formats, the component ordering is specified (Y, followed by U
- * then V), but the exact Linear layout is undefined.
- * These formats can only be used with a non-Linear modifier.
- */
-#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
-#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
/*
* 2 plane RGB + A
@@ -238,34 +142,6 @@
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [10:6] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
- */
-#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [10:6] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
- */
-#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y:x [12:4] little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
- */
-#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
-
-/*
- * 2 plane YCbCr MSB aligned
- * index 0 = Y plane, [15:0] Y little endian
- * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
- */
-#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
-
-/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
@@ -307,9 +183,6 @@
#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
-#define DRM_FORMAT_MOD_VENDOR_ARM 0x08
-#define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
-
/* add more to the end as needed */
#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
@@ -381,7 +254,7 @@
* This is a tiled layout using 4Kb tiles in row-major layout.
* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
* are arranged in four groups (two wide, two high) with column-major layout.
- * Each group therefore consists out of four 256 byte units, which are also laid
+ * Each group therefore consits out of four 256 byte units, which are also laid
* out as 2x2 column-major.
* 256 byte units are made out of four 64 byte blocks of pixels, producing
* either a square block or a 2:1 unit.
@@ -425,28 +298,6 @@
*/
#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
-/*
- * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
- *
- * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
- * layout. For YCbCr formats Cb/Cr components are taken in such a way that
- * they correspond to their 16x16 luma block.
- */
-#define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
-
-/*
- * Qualcomm Compressed Format
- *
- * Refers to a compressed variant of the base format that is compressed.
- * Implementation may be platform and base-format specific.
- *
- * Each macrotile consists of m x n (mostly 4 x 4) tiles.
- * Pixel data pitch/stride is aligned with macrotile width.
- * Pixel data height is aligned with macrotile height.
- * Entire pixel data buffer is aligned with 4k(bytes).
- */
-#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
-
/* Vivante framebuffer modifiers */
/*
@@ -534,23 +385,6 @@
fourcc_mod_code(NVIDIA, 0x15)
/*
- * Some Broadcom modifiers take parameters, for example the number of
- * vertical lines in the image. Reserve the lower 32 bits for modifier
- * type, and the next 24 bits for parameters. Top 8 bits are the
- * vendor code.
- */
-#define __fourcc_mod_broadcom_param_shift 8
-#define __fourcc_mod_broadcom_param_bits 48
-#define fourcc_mod_broadcom_code(val, params) \
- fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
-#define fourcc_mod_broadcom_param(m) \
- ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
- ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
-#define fourcc_mod_broadcom_mod(m) \
- ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
- __fourcc_mod_broadcom_param_shift))
-
-/*
* Broadcom VC4 "T" format
*
* This is the primary layout that the V3D GPU can texture from (it
@@ -571,191 +405,6 @@
*/
#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
-/*
- * Broadcom SAND format
- *
- * This is the native format that the H.264 codec block uses. For VC4
- * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
- *
- * The image can be considered to be split into columns, and the
- * columns are placed consecutively into memory. The width of those
- * columns can be either 32, 64, 128, or 256 pixels, but in practice
- * only 128 pixel columns are used.
- *
- * The pitch between the start of each column is set to optimally
- * switch between SDRAM banks. This is passed as the number of lines
- * of column width in the modifier (we can't use the stride value due
- * to various core checks that look at it , so you should set the
- * stride to width*cpp).
- *
- * Note that the column height for this format modifier is the same
- * for all of the planes, assuming that each column contains both Y
- * and UV. Some SAND-using hardware stores UV in a separate tiled
- * image from Y to reduce the column height, which is not supported
- * with these modifiers.
- */
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(2, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(3, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(4, v)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
- fourcc_mod_broadcom_code(5, v)
-
-#define DRM_FORMAT_MOD_BROADCOM_SAND32 \
- DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND64 \
- DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND128 \
- DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
-#define DRM_FORMAT_MOD_BROADCOM_SAND256 \
- DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
-
-/* Broadcom UIF format
- *
- * This is the common format for the current Broadcom multimedia
- * blocks, including V3D 3.x and newer, newer video codecs, and
- * displays.
- *
- * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
- * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
- * stored in columns, with padding between the columns to ensure that
- * moving from one column to the next doesn't hit the same SDRAM page
- * bank.
- *
- * To calculate the padding, it is assumed that each hardware block
- * and the software driving it knows the platform's SDRAM page size,
- * number of banks, and XOR address, and that it's identical between
- * all blocks using the format. This tiling modifier will use XOR as
- * necessary to reduce the padding. If a hardware block can't do XOR,
- * the assumption is that a no-XOR tiling modifier will be created.
- */
-#define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
-
-/*
- * Arm Framebuffer Compression (AFBC) modifiers
- *
- * AFBC is a proprietary lossless image compression protocol and format.
- * It provides fine-grained random access and minimizes the amount of data
- * transferred between IP blocks.
- *
- * AFBC has several features which may be supported and/or used, which are
- * represented using bits in the modifier. Not all combinations are valid,
- * and different devices or use-cases may support different combinations.
- *
- * Further information on the use of AFBC modifiers can be found in
- * Documentation/gpu/afbc.rst
- */
-#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)
-
-/*
- * AFBC superblock size
- *
- * Indicates the superblock size(s) used for the AFBC buffer. The buffer
- * size (in pixels) must be aligned to a multiple of the superblock size.
- * Four lowest significant bits(LSBs) are reserved for block size.
- *
- * Where one superblock size is specified, it applies to all planes of the
- * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
- * the first applies to the Luma plane and the second applies to the Chroma
- * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
- * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
- */
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
-#define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
-
-/*
- * AFBC lossless colorspace transform
- *
- * Indicates that the buffer makes use of the AFBC lossless colorspace
- * transform.
- */
-#define AFBC_FORMAT_MOD_YTR (1ULL << 4)
-
-/*
- * AFBC block-split
- *
- * Indicates that the payload of each superblock is split. The second
- * half of the payload is positioned at a predefined offset from the start
- * of the superblock payload.
- */
-#define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
-
-/*
- * AFBC sparse layout
- *
- * This flag indicates that the payload of each superblock must be stored at a
- * predefined position relative to the other superblocks in the same AFBC
- * buffer. This order is the same order used by the header buffer. In this mode
- * each superblock is given the same amount of space as an uncompressed
- * superblock of the particular format would require, rounding up to the next
- * multiple of 128 bytes in size.
- */
-#define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
-
-/*
- * AFBC copy-block restrict
- *
- * Buffers with this flag must obey the copy-block restriction. The restriction
- * is such that there are no copy-blocks referring across the border of 8x8
- * blocks. For the subsampled data the 8x8 limitation is also subsampled.
- */
-#define AFBC_FORMAT_MOD_CBR (1ULL << 7)
-
-/*
- * AFBC tiled layout
- *
- * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
- * superblocks inside a tile are stored together in memory. 8x8 tiles are used
- * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
- * larger bpp formats. The order between the tiles is scan line.
- * When the tiled layout is used, the buffer size (in pixels) must be aligned
- * to the tile size.
- */
-#define AFBC_FORMAT_MOD_TILED (1ULL << 8)
-
-/*
- * AFBC solid color blocks
- *
- * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
- * can be reduced if a whole superblock is a single color.
- */
-#define AFBC_FORMAT_MOD_SC (1ULL << 9)
-
-/*
- * AFBC double-buffer
- *
- * Indicates that the buffer is allocated in a layout safe for front-buffer
- * rendering.
- */
-#define AFBC_FORMAT_MOD_DB (1ULL << 10)
-
-/*
- * AFBC buffer content hints
- *
- * Indicates that the buffer includes per-superblock content hints.
- */
-#define AFBC_FORMAT_MOD_BCH (1ULL << 11)
-
-/*
- * Allwinner tiled modifier
- *
- * This tiling mode is implemented by the VPU found on all Allwinner platforms,
- * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
- * planes.
- *
- * With this tiling, the luminance samples are disposed in tiles representing
- * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
- * The pixel order in each tile is linear and the tiles are disposed linearly,
- * both in row-major order.
- */
-#define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
-
#if defined(__cplusplus)
}
#endif
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 5fe6c64..74368de 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -33,6 +33,7 @@
extern "C" {
#endif
+#define DRM_DISPLAY_INFO_LEN 32
#define DRM_CONNECTOR_NAME_LEN 32
#define DRM_DISPLAY_MODE_LEN 32
#define DRM_PROP_NAME_LEN 32
@@ -45,10 +46,6 @@
#define DRM_MODE_TYPE_USERDEF (1<<5)
#define DRM_MODE_TYPE_DRIVER (1<<6)
-#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | \
- DRM_MODE_TYPE_USERDEF | \
- DRM_MODE_TYPE_DRIVER)
-
/* Video mode flags */
/* bit compatible with the xrandr RR_ definitions (bits 0-13)
*
@@ -92,15 +89,6 @@
#define DRM_MODE_PICTURE_ASPECT_NONE 0
#define DRM_MODE_PICTURE_ASPECT_4_3 1
#define DRM_MODE_PICTURE_ASPECT_16_9 2
-#define DRM_MODE_PICTURE_ASPECT_64_27 3
-#define DRM_MODE_PICTURE_ASPECT_256_135 4
-
-/* Content type options */
-#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
-#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
-#define DRM_MODE_CONTENT_TYPE_PHOTO 2
-#define DRM_MODE_CONTENT_TYPE_CINEMA 3
-#define DRM_MODE_CONTENT_TYPE_GAME 4
/* Aspect ratio flag bitmask (4 bits 22:19) */
#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
@@ -110,24 +98,6 @@
(DRM_MODE_PICTURE_ASPECT_4_3<<19)
#define DRM_MODE_FLAG_PIC_AR_16_9 \
(DRM_MODE_PICTURE_ASPECT_16_9<<19)
-#define DRM_MODE_FLAG_PIC_AR_64_27 \
- (DRM_MODE_PICTURE_ASPECT_64_27<<19)
-#define DRM_MODE_FLAG_PIC_AR_256_135 \
- (DRM_MODE_PICTURE_ASPECT_256_135<<19)
-
-#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | \
- DRM_MODE_FLAG_NHSYNC | \
- DRM_MODE_FLAG_PVSYNC | \
- DRM_MODE_FLAG_NVSYNC | \
- DRM_MODE_FLAG_INTERLACE | \
- DRM_MODE_FLAG_DBLSCAN | \
- DRM_MODE_FLAG_CSYNC | \
- DRM_MODE_FLAG_PCSYNC | \
- DRM_MODE_FLAG_NCSYNC | \
- DRM_MODE_FLAG_HSKEW | \
- DRM_MODE_FLAG_DBLCLK | \
- DRM_MODE_FLAG_CLKDIV2 | \
- DRM_MODE_FLAG_3D_MASK)
/* DPMS flags */
/* bit compatible with the xorg definitions. */
@@ -185,9 +155,8 @@
/*
* DRM_MODE_REFLECT_<axis>
*
- * Signals that the contents of a drm plane is reflected along the <axis> axis,
+ * Signals that the contents of a drm plane is reflected in the <axis> axis,
* in the same way as mirroring.
- * See kerneldoc chapter "Plane Composition Properties" for more details.
*
* This define is provided as a convenience, looking up the property id
* using the name->prop id lookup is the preferred method.
@@ -204,6 +173,19 @@
DRM_MODE_REFLECT_X | \
DRM_MODE_REFLECT_Y)
+
+/*
+ * Legacy definitions for old code that doesn't use
+ * the above mask definitions. Don't use in future code.
+ */
+/* rotation property bits */
+#define DRM_ROTATE_0 0
+#define DRM_ROTATE_90 1
+#define DRM_ROTATE_180 2
+#define DRM_ROTATE_270 3
+#define DRM_REFLECT_X 4
+#define DRM_REFLECT_Y 5
+
/* Content Protection Flags */
#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
@@ -351,7 +333,6 @@
#define DRM_MODE_CONNECTOR_VIRTUAL 15
#define DRM_MODE_CONNECTOR_DSI 16
#define DRM_MODE_CONNECTOR_DPI 17
-#define DRM_MODE_CONNECTOR_WRITEBACK 18
struct drm_mode_get_connector {
@@ -402,7 +383,7 @@
/* the PROP_ATOMIC flag is used to hide properties from userspace that
* is not aware of atomic properties. This is mostly to work around
* older userspace (DDX drivers) that read/write each prop they find,
- * without being aware that this could be triggering a lengthy modeset.
+ * witout being aware that this could be triggering a lengthy modeset.
*/
#define DRM_MODE_PROP_ATOMIC 0x80000000
@@ -621,8 +602,7 @@
struct drm_color_lut {
/*
- * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
- * 0xffff == 1.0.
+ * Data is U0.16 fixed point format.
*/
__u16 red;
__u16 green;
@@ -888,25 +868,6 @@
__u32 lessee_id;
};
-/**
- * struct drm_mode_rect - Two dimensional rectangle.
- * @x1: Horizontal starting coordinate (inclusive).
- * @y1: Vertical starting coordinate (inclusive).
- * @x2: Horizontal ending coordinate (exclusive).
- * @y2: Vertical ending coordinate (exclusive).
- *
- * With drm subsystem using struct drm_rect to manage rectangular area this
- * export it to user-space.
- *
- * Currently used by drm_mode_atomic blob property FB_DAMAGE_CLIPS.
- */
-struct drm_mode_rect {
- __s32 x1;
- __s32 y1;
- __s32 x2;
- __s32 y2;
-};
-
#if defined(__cplusplus)
}
#endif
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 72afd94..16e452a 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -63,28 +63,6 @@
#define I915_RESET_UEVENT "RESET"
/*
- * i915_user_extension: Base class for defining a chain of extensions
- *
- * Many interfaces need to grow over time. In most cases we can simply
- * extend the struct and have userspace pass in more data. Another option,
- * as demonstrated by Vulkan's approach to providing extensions for forward
- * and backward compatibility, is to use a list of optional structs to
- * provide those extra details.
- *
- * The key advantage to using an extension chain is that it allows us to
- * redefine the interface more easily than an ever growing struct of
- * increasing complexity, and for large parts of that interface to be
- * entirely optional. The downside is more pointer chasing; chasing across
- * the boundary with pointers encapsulated inside u64.
- */
-struct i915_user_extension {
- __u64 next_extension;
- __u32 name;
- __u32 flags; /* All undefined bits must be zero. */
- __u32 rsvd[4]; /* Reserved for future use; must be zero. */
-};
-
-/*
* MOCS indexes used for GPU surfaces, defining the cacheability of the
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
*/
@@ -121,8 +99,6 @@
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
-
I915_ENGINE_CLASS_INVALID = -1
};
@@ -343,7 +319,6 @@
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
-/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -392,7 +367,6 @@
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
-#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@@ -438,14 +412,6 @@
int irq_seq;
} drm_i915_irq_wait_t;
-/*
- * Different modes of per-process Graphics Translation Table,
- * see I915_PARAM_HAS_ALIASING_PPGTT
- */
-#define I915_GEM_PPGTT_NONE 0
-#define I915_GEM_PPGTT_ALIASING 1
-#define I915_GEM_PPGTT_FULL 2
-
/* Ioctl to query kernel params:
*/
#define I915_PARAM_IRQ_ACTIVE 1
@@ -502,7 +468,6 @@
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
-#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_PARAM_HUC_STATUS 42
@@ -520,7 +485,7 @@
#define I915_PARAM_HAS_EXEC_FENCE 44
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
- * user specified buffers for post-mortem debugging of GPU hangs. See
+ * user specified bufffers for post-mortem debugging of GPU hangs. See
* EXEC_OBJECT_CAPTURE.
*/
#define I915_PARAM_HAS_EXEC_CAPTURE 45
@@ -564,30 +529,6 @@
*/
#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
-/*
- * Once upon a time we supposed that writes through the GGTT would be
- * immediately in physical memory (once flushed out of the CPU path). However,
- * on a few different processors and chipsets, this is not necessarily the case
- * as the writes appear to be buffered internally. Thus a read of the backing
- * storage (physical memory) via a different path (with different physical tags
- * to the indirect write via the GGTT) will see stale values from before
- * the GGTT write. Inside the kernel, we can for the most part keep track of
- * the different read/write domains in use (e.g. set-domain), but the assumption
- * of coherency is baked into the ABI, hence reporting its true state in this
- * parameter.
- *
- * Reports true when writes via mmap_gtt are immediately visible following an
- * lfence to flush the WCB.
- *
- * Reports false when writes via mmap_gtt are indeterminately delayed in an in
- * internal buffer and are _not_ immediately visible to third parties accessing
- * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
- * communications channel when reporting false is strongly disadvised.
- */
-#define I915_PARAM_MMAP_GTT_COHERENT 52
-
-/* Must be kept compact -- no holes and well documented */
-
typedef struct drm_i915_getparam {
__s32 param;
/*
@@ -603,7 +544,6 @@
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
#define I915_SETPARAM_NUM_USED_FENCES 4
-/* Must be kept compact -- no holes */
typedef struct drm_i915_setparam {
int param;
@@ -1002,7 +942,7 @@
* struct drm_i915_gem_exec_fence *fences.
*/
__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK (0x3f)
+#define I915_EXEC_RING_MASK (7<<0)
#define I915_EXEC_DEFAULT (0<<0)
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
@@ -1150,34 +1090,32 @@
* as busy may become idle before the ioctl is completed.
*
* Furthermore, if the object is busy, which engine is busy is only
- * provided as a guide and only indirectly by reporting its class
- * (there may be more than one engine in each class). There are race
- * conditions which prevent the report of which engines are busy from
- * being always accurate. However, the converse is not true. If the
- * object is idle, the result of the ioctl, that all engines are idle,
- * is accurate.
+ * provided as a guide. There are race conditions which prevent the
+ * report of which engines are busy from being always accurate.
+ * However, the converse is not true. If the object is idle, the
+ * result of the ioctl, that all engines are idle, is accurate.
*
* The returned dword is split into two fields to indicate both
- * the engine classess on which the object is being read, and the
- * engine class on which it is currently being written (if any).
+ * the engines on which the object is being read, and the
+ * engine on which it is currently being written (if any).
*
* The low word (bits 0:15) indicate if the object is being written
* to by any engine (there can only be one, as the GEM implicit
* synchronisation rules force writes to be serialised). Only the
- * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
- * 1 not 0 etc) for the last write is reported.
+ * engine for the last write is reported.
*
- * The high word (bits 16:31) are a bitmask of which engines classes
- * are currently reading from the object. Multiple engines may be
+ * The high word (bits 16:31) are a bitmask of which engines are
+ * currently reading from the object. Multiple engines may be
* reading from the object simultaneously.
*
- * The value of each engine class is the same as specified in the
- * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
- * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
+ * The value of each engine is the same as specified in the
+ * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
+ * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
+ * the I915_EXEC_RENDER engine for execution, and so it is never
* reported as active itself. Some hardware may have parallel
* execution engines, e.g. multiple media engines, which are
- * mapped to the same class identifier and so are not separately
- * reported for busyness.
+ * mapped to the same identifier in the EXECBUFFER2 ioctl and
+ * so are not separately reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@@ -1220,7 +1158,7 @@
__u32 handle;
/**
- * Caching level to apply or return value
+ * Cacheing level to apply or return value
*
* bits0-15 are for generic caching control (i.e. the above defined
* values). bits16-31 are reserved for platform-specific variations
@@ -1444,125 +1382,9 @@
};
struct drm_i915_gem_context_create {
- __u32 ctx_id; /* output: id of new context*/
- __u32 pad;
-};
-
-struct drm_i915_gem_context_create_ext {
- __u32 ctx_id; /* output: id of new context*/
- __u32 flags;
-#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
-#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
- (-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
- __u64 extensions;
-};
-
-struct drm_i915_gem_context_param {
+ /* output: id of new context*/
__u32 ctx_id;
- __u32 size;
- __u64 param;
-#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
-#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
-#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
-#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
-#define I915_CONTEXT_PARAM_BANNABLE 0x5
-#define I915_CONTEXT_PARAM_PRIORITY 0x6
-#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
-#define I915_CONTEXT_DEFAULT_PRIORITY 0
-#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
- /*
- * When using the following param, value should be a pointer to
- * drm_i915_gem_context_param_sseu.
- */
-#define I915_CONTEXT_PARAM_SSEU 0x7
-
-/*
- * Not all clients may want to attempt automatic recover of a context after
- * a hang (for example, some clients may only submit very small incremental
- * batches relying on known logical state of previous batches which will never
- * recover correctly and each attempt will hang), and so would prefer that
- * the context is forever banned instead.
- *
- * If set to false (0), after a reset, subsequent (and in flight) rendering
- * from this context is discarded, and the client will need to create a new
- * context to use instead.
- *
- * If set to true (1), the kernel will automatically attempt to recover the
- * context by skipping the hanging batch and executing the next batch starting
- * from the default context state (discarding the incomplete logical context
- * state lost due to the reset).
- *
- * On creation, all new contexts are marked as recoverable.
- */
-#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
-/* Must be kept compact -- no holes and well documented */
-
- __u64 value;
-};
-
-/**
- * Context SSEU programming
- *
- * It may be necessary for either functional or performance reason to configure
- * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
- * Sub-slice/EU).
- *
- * This is done by configuring SSEU configuration using the below
- * @struct drm_i915_gem_context_param_sseu for every supported engine which
- * userspace intends to use.
- *
- * Not all GPUs or engines support this functionality in which case an error
- * code -ENODEV will be returned.
- *
- * Also, flexibility of possible SSEU configuration permutations varies between
- * GPU generations and software imposed limitations. Requesting such a
- * combination will return an error code of -EINVAL.
- *
- * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
- * favour of a single global setting.
- */
-struct drm_i915_gem_context_param_sseu {
- /*
- * Engine class & instance to be configured or queried.
- */
- __u16 engine_class;
- __u16 engine_instance;
-
- /*
- * Unused for now. Must be cleared to zero.
- */
- __u32 flags;
-
- /*
- * Mask of slices to enable for the context. Valid values are a subset
- * of the bitmask value returned for I915_PARAM_SLICE_MASK.
- */
- __u64 slice_mask;
-
- /*
- * Mask of subslices to enable for the context. Valid values are a
- * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
- */
- __u64 subslice_mask;
-
- /*
- * Minimum/Maximum number of EUs to enable per subslice for the
- * context. min_eus_per_subslice must be inferior or equal to
- * max_eus_per_subslice.
- */
- __u16 min_eus_per_subslice;
- __u16 max_eus_per_subslice;
-
- /*
- * Unused for now. Must be cleared to zero.
- */
- __u32 rsvd;
-};
-
-struct drm_i915_gem_context_create_ext_setparam {
-#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
- struct i915_user_extension base;
- struct drm_i915_gem_context_param param;
+ __u32 pad;
};
struct drm_i915_gem_context_destroy {
@@ -1570,33 +1392,6 @@
__u32 pad;
};
-/*
- * DRM_I915_GEM_VM_CREATE -
- *
- * Create a new virtual memory address space (ppGTT) for use within a context
- * on the same file. Extensions can be provided to configure exactly how the
- * address space is setup upon creation.
- *
- * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
- * returned in the outparam @id.
- *
- * No flags are defined, with all bits reserved and must be zero.
- *
- * An extension chain maybe provided, starting with @extensions, and terminated
- * by the @next_extension being 0. Currently, no extensions are defined.
- *
- * DRM_I915_GEM_VM_DESTROY -
- *
- * Destroys a previously created VM id, specified in @id.
- *
- * No extensions or flags are allowed currently, and so must be zero.
- */
-struct drm_i915_gem_vm_control {
- __u64 extensions;
- __u32 flags;
- __u32 vm_id;
-};
-
struct drm_i915_reg_read {
/*
* Register offset.
@@ -1609,7 +1404,6 @@
__u64 val; /* Return value */
};
-
/* Known registers:
*
* Render engine timestamp - 0x2358 + 64bit - gen7+
@@ -1649,6 +1443,22 @@
__u32 handle;
};
+struct drm_i915_gem_context_param {
+ __u32 ctx_id;
+ __u32 size;
+ __u64 param;
+#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
+#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
+#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
+#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
+#define I915_CONTEXT_PARAM_BANNABLE 0x5
+#define I915_CONTEXT_PARAM_PRIORITY 0x6
+#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
+#define I915_CONTEXT_DEFAULT_PRIORITY 0
+#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
+ __u64 value;
+};
+
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
@@ -1810,7 +1620,6 @@
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
-/* Must be kept compact -- no holes and well documented */
/*
* When set to zero by userspace, this is filled with the size of the
diff --git a/include/drm/nouveau_class.h b/include/drm/nouveau_class.h
new file mode 100644
index 0000000..8d63877
--- /dev/null
+++ b/include/drm/nouveau_class.h
@@ -0,0 +1,651 @@
+#ifndef __NVIF_CLASS_H__
+#define __NVIF_CLASS_H__
+
+/*******************************************************************************
+ * class identifiers
+ ******************************************************************************/
+
+/* the below match nvidia-assigned (either in hw, or sw) class numbers */
+#define NV_DEVICE 0x00000080
+
+#define NV_DMA_FROM_MEMORY 0x00000002
+#define NV_DMA_TO_MEMORY 0x00000003
+#define NV_DMA_IN_MEMORY 0x0000003d
+
+#define FERMI_TWOD_A 0x0000902d
+
+#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d
+
+#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
+#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
+
+#define NV04_DISP 0x00000046
+
+#define NV03_CHANNEL_DMA 0x0000006b
+#define NV10_CHANNEL_DMA 0x0000006e
+#define NV17_CHANNEL_DMA 0x0000176e
+#define NV40_CHANNEL_DMA 0x0000406e
+#define NV50_CHANNEL_DMA 0x0000506e
+#define G82_CHANNEL_DMA 0x0000826e
+
+#define NV50_CHANNEL_GPFIFO 0x0000506f
+#define G82_CHANNEL_GPFIFO 0x0000826f
+#define FERMI_CHANNEL_GPFIFO 0x0000906f
+#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
+#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
+
+#define NV50_DISP 0x00005070
+#define G82_DISP 0x00008270
+#define GT200_DISP 0x00008370
+#define GT214_DISP 0x00008570
+#define GT206_DISP 0x00008870
+#define GF110_DISP 0x00009070
+#define GK104_DISP 0x00009170
+#define GK110_DISP 0x00009270
+#define GM107_DISP 0x00009470
+#define GM204_DISP 0x00009570
+
+#define NV50_DISP_CURSOR 0x0000507a
+#define G82_DISP_CURSOR 0x0000827a
+#define GT214_DISP_CURSOR 0x0000857a
+#define GF110_DISP_CURSOR 0x0000907a
+#define GK104_DISP_CURSOR 0x0000917a
+
+#define NV50_DISP_OVERLAY 0x0000507b
+#define G82_DISP_OVERLAY 0x0000827b
+#define GT214_DISP_OVERLAY 0x0000857b
+#define GF110_DISP_OVERLAY 0x0000907b
+#define GK104_DISP_OVERLAY 0x0000917b
+
+#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
+#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
+#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
+#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
+#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
+#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
+#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
+
+#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
+#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
+#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
+#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
+#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
+#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
+#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
+#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
+#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
+#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
+
+#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
+#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
+#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
+#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
+#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
+#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
+
+#define FERMI_A 0x00009097
+#define FERMI_B 0x00009197
+#define FERMI_C 0x00009297
+
+#define KEPLER_A 0x0000a097
+#define KEPLER_B 0x0000a197
+#define KEPLER_C 0x0000a297
+
+#define MAXWELL_A 0x0000b097
+#define MAXWELL_B 0x0000b197
+
+#define FERMI_COMPUTE_A 0x000090c0
+#define FERMI_COMPUTE_B 0x000091c0
+
+#define KEPLER_COMPUTE_A 0x0000a0c0
+#define KEPLER_COMPUTE_B 0x0000a1c0
+
+#define MAXWELL_COMPUTE_A 0x0000b0c0
+#define MAXWELL_COMPUTE_B 0x0000b1c0
+
+#define MAXWELL_DMA_COPY_A 0x0000b0b5
+
+/*******************************************************************************
+ * client
+ ******************************************************************************/
+
+#define NV_CLIENT_DEVLIST 0x00
+
+struct nv_client_devlist_v0 {
+ __u8 version;
+ __u8 count;
+ __u8 pad02[6];
+ __u64 device[];
+};
+
+
+/*******************************************************************************
+ * device
+ ******************************************************************************/
+
+struct nv_device_v0 {
+ __u8 version;
+ __u8 pad01[7];
+ __u64 device; /* device identifier, ~0 for client default */
+#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
+#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
+#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
+#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
+#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
+#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
+#define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL
+#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
+#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
+#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
+#define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL
+#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL
+#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL
+#define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
+#define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL
+ __u64 disable; /* disable particular subsystems */
+ __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
+};
+
+#define NV_DEVICE_V0_INFO 0x00
+#define NV_DEVICE_V0_ZCULL_INFO 0x01
+
+struct nv_device_info_v0 {
+ __u8 version;
+#define NV_DEVICE_INFO_V0_IGP 0x00
+#define NV_DEVICE_INFO_V0_PCI 0x01
+#define NV_DEVICE_INFO_V0_AGP 0x02
+#define NV_DEVICE_INFO_V0_PCIE 0x03
+#define NV_DEVICE_INFO_V0_SOC 0x04
+ __u8 platform;
+ __u16 chipset; /* from NV_PMC_BOOT_0 */
+ __u8 revision; /* from NV_PMC_BOOT_0 */
+#define NV_DEVICE_INFO_V0_TNT 0x01
+#define NV_DEVICE_INFO_V0_CELSIUS 0x02
+#define NV_DEVICE_INFO_V0_KELVIN 0x03
+#define NV_DEVICE_INFO_V0_RANKINE 0x04
+#define NV_DEVICE_INFO_V0_CURIE 0x05
+#define NV_DEVICE_INFO_V0_TESLA 0x06
+#define NV_DEVICE_INFO_V0_FERMI 0x07
+#define NV_DEVICE_INFO_V0_KEPLER 0x08
+#define NV_DEVICE_INFO_V0_MAXWELL 0x09
+ __u8 family;
+ __u8 pad06[2];
+ __u64 ram_size;
+ __u64 ram_user;
+};
+
+struct nv_device_zcull_info_v0 {
+ __u8 version;
+ __u8 pad03[3];
+ __u32 image_size;
+ __u32 width_align_pixels;
+ __u32 height_align_pixels;
+ __u32 pixel_squares_by_aliquots;
+ __u32 aliquot_total;
+ __u32 region_byte_multiplier;
+ __u32 region_header_size;
+ __u32 subregion_header_size;
+ __u32 subregion_width_align_pixels;
+ __u32 subregion_height_align_pixels;
+ __u32 subregion_count;
+};
+
+/*******************************************************************************
+ * context dma
+ ******************************************************************************/
+
+struct nv_dma_v0 {
+ __u8 version;
+#define NV_DMA_V0_TARGET_VM 0x00
+#define NV_DMA_V0_TARGET_VRAM 0x01
+#define NV_DMA_V0_TARGET_PCI 0x02
+#define NV_DMA_V0_TARGET_PCI_US 0x03
+#define NV_DMA_V0_TARGET_AGP 0x04
+ __u8 target;
+#define NV_DMA_V0_ACCESS_VM 0x00
+#define NV_DMA_V0_ACCESS_RD 0x01
+#define NV_DMA_V0_ACCESS_WR 0x02
+#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
+ __u8 access;
+ __u8 pad03[5];
+ __u64 start;
+ __u64 limit;
+ /* ... chipset-specific class data */
+};
+
+struct nv50_dma_v0 {
+ __u8 version;
+#define NV50_DMA_V0_PRIV_VM 0x00
+#define NV50_DMA_V0_PRIV_US 0x01
+#define NV50_DMA_V0_PRIV__S 0x02
+ __u8 priv;
+#define NV50_DMA_V0_PART_VM 0x00
+#define NV50_DMA_V0_PART_256 0x01
+#define NV50_DMA_V0_PART_1KB 0x02
+ __u8 part;
+#define NV50_DMA_V0_COMP_NONE 0x00
+#define NV50_DMA_V0_COMP_1 0x01
+#define NV50_DMA_V0_COMP_2 0x02
+#define NV50_DMA_V0_COMP_VM 0x03
+ __u8 comp;
+#define NV50_DMA_V0_KIND_PITCH 0x00
+#define NV50_DMA_V0_KIND_VM 0x7f
+ __u8 kind;
+ __u8 pad05[3];
+};
+
+struct gf100_dma_v0 {
+ __u8 version;
+#define GF100_DMA_V0_PRIV_VM 0x00
+#define GF100_DMA_V0_PRIV_US 0x01
+#define GF100_DMA_V0_PRIV__S 0x02
+ __u8 priv;
+#define GF100_DMA_V0_KIND_PITCH 0x00
+#define GF100_DMA_V0_KIND_VM 0xff
+ __u8 kind;
+ __u8 pad03[5];
+};
+
+struct gf110_dma_v0 {
+ __u8 version;
+#define GF110_DMA_V0_PAGE_LP 0x00
+#define GF110_DMA_V0_PAGE_SP 0x01
+ __u8 page;
+#define GF110_DMA_V0_KIND_PITCH 0x00
+#define GF110_DMA_V0_KIND_VM 0xff
+ __u8 kind;
+ __u8 pad03[5];
+};
+
+
+/*******************************************************************************
+ * perfmon
+ ******************************************************************************/
+
+struct nvif_perfctr_v0 {
+ __u8 version;
+ __u8 pad01[1];
+ __u16 logic_op;
+ __u8 pad04[4];
+ char name[4][64];
+};
+
+#define NVIF_PERFCTR_V0_QUERY 0x00
+#define NVIF_PERFCTR_V0_SAMPLE 0x01
+#define NVIF_PERFCTR_V0_READ 0x02
+
+struct nvif_perfctr_query_v0 {
+ __u8 version;
+ __u8 pad01[3];
+ __u32 iter;
+ char name[64];
+};
+
+struct nvif_perfctr_sample {
+};
+
+struct nvif_perfctr_read_v0 {
+ __u8 version;
+ __u8 pad01[7];
+ __u32 ctr;
+ __u32 clk;
+};
+
+
+/*******************************************************************************
+ * device control
+ ******************************************************************************/
+
+#define NVIF_CONTROL_PSTATE_INFO 0x00
+#define NVIF_CONTROL_PSTATE_ATTR 0x01
+#define NVIF_CONTROL_PSTATE_USER 0x02
+
+struct nvif_ustate {
+ __s8 min;
+ __s8 max;
+};
+
+struct nvif_control_pstate_info_v0 {
+ __u8 version;
+ __u8 count; /* out: number of power states */
+#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
+#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
+ struct {
+ struct nvif_ustate dc; // pwrsrc == 0
+ struct nvif_ustate ac; // pwrsrc == 1
+ } ustate; /* out: target pstate index */
+ __s8 pwrsrc; /* out: current power source */
+#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
+#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
+ __s8 pstate; /* out: current pstate index */
+ __u8 pad06[2];
+};
+
+struct nvif_control_pstate_attr_v0 {
+ __u8 version;
+#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
+ __s8 state; /* in: index of pstate to query
+ * out: pstate identifier
+ */
+ __u8 index; /* in: index of attribute to query
+ * out: index of next attribute, or 0 if no more
+ */
+ __u8 pad03[5];
+ __u32 min;
+ __u32 max;
+ char name[32];
+ char unit[16];
+};
+
+struct nvif_control_pstate_user_v0 {
+ __u8 version;
+#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
+#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
+ struct nvif_ustate ustate; /* in: pstate identifier */
+ __s8 pwrsrc; /* in: target power source */
+ __u8 pad03[5];
+};
+
+
+/*******************************************************************************
+ * DMA FIFO channels
+ ******************************************************************************/
+
+struct nv03_channel_dma_v0 {
+ __u8 version;
+ __u8 chid;
+ __u8 pad02[2];
+ __u32 pushbuf;
+ __u64 offset;
+};
+
+#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
+
+/*******************************************************************************
+ * GPFIFO channels
+ ******************************************************************************/
+
+struct nv50_channel_gpfifo_v0 {
+ __u8 version;
+ __u8 chid;
+ __u8 pad01[6];
+ __u32 pushbuf;
+ __u32 ilength;
+ __u64 ioffset;
+};
+
+struct kepler_channel_gpfifo_a_v0 {
+ __u8 version;
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
+ __u8 engine;
+ __u16 chid;
+ __u8 pad04[4];
+ __u32 pushbuf;
+ __u32 ilength;
+ __u64 ioffset;
+};
+
+#define CHANNEL_GPFIFO_ERROR_NOTIFIER_EEVENT 0x01
+
+/*******************************************************************************
+ * legacy display
+ ******************************************************************************/
+
+#define NV04_DISP_NTFY_VBLANK 0x00
+#define NV04_DISP_NTFY_CONN 0x01
+
+struct nv04_disp_mthd_v0 {
+ __u8 version;
+#define NV04_DISP_SCANOUTPOS 0x00
+ __u8 method;
+ __u8 head;
+ __u8 pad03[5];
+};
+
+struct nv04_disp_scanoutpos_v0 {
+ __u8 version;
+ __u8 pad01[7];
+ __s64 time[2];
+ __u16 vblanks;
+ __u16 vblanke;
+ __u16 vtotal;
+ __u16 vline;
+ __u16 hblanks;
+ __u16 hblanke;
+ __u16 htotal;
+ __u16 hline;
+};
+
+/*******************************************************************************
+ * display
+ ******************************************************************************/
+
+#define NV50_DISP_MTHD 0x00
+
+struct nv50_disp_mthd_v0 {
+ __u8 version;
+#define NV50_DISP_SCANOUTPOS 0x00
+ __u8 method;
+ __u8 head;
+ __u8 pad03[5];
+};
+
+struct nv50_disp_mthd_v1 {
+ __u8 version;
+#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
+#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
+#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
+#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
+#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
+#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
+#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
+#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
+ __u8 method;
+ __u16 hasht;
+ __u16 hashm;
+ __u8 pad06[2];
+};
+
+struct nv50_disp_dac_pwr_v0 {
+ __u8 version;
+ __u8 state;
+ __u8 data;
+ __u8 vsync;
+ __u8 hsync;
+ __u8 pad05[3];
+};
+
+struct nv50_disp_dac_load_v0 {
+ __u8 version;
+ __u8 load;
+ __u8 pad02[2];
+ __u32 data;
+};
+
+struct nv50_disp_sor_pwr_v0 {
+ __u8 version;
+ __u8 state;
+ __u8 pad02[6];
+};
+
+struct nv50_disp_sor_hda_eld_v0 {
+ __u8 version;
+ __u8 pad01[7];
+ __u8 data[];
+};
+
+struct nv50_disp_sor_hdmi_pwr_v0 {
+ __u8 version;
+ __u8 state;
+ __u8 max_ac_packet;
+ __u8 rekey;
+ __u8 pad04[4];
+};
+
+struct nv50_disp_sor_lvds_script_v0 {
+ __u8 version;
+ __u8 pad01[1];
+ __u16 script;
+ __u8 pad04[4];
+};
+
+struct nv50_disp_sor_dp_pwr_v0 {
+ __u8 version;
+ __u8 state;
+ __u8 pad02[6];
+};
+
+struct nv50_disp_pior_pwr_v0 {
+ __u8 version;
+ __u8 state;
+ __u8 type;
+ __u8 pad03[5];
+};
+
+/* core */
+struct nv50_disp_core_channel_dma_v0 {
+ __u8 version;
+ __u8 pad01[3];
+ __u32 pushbuf;
+};
+
+#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
+
+/* cursor immediate */
+struct nv50_disp_cursor_v0 {
+ __u8 version;
+ __u8 head;
+ __u8 pad02[6];
+};
+
+#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
+
+/* base */
+struct nv50_disp_base_channel_dma_v0 {
+ __u8 version;
+ __u8 pad01[2];
+ __u8 head;
+ __u32 pushbuf;
+};
+
+#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
+
+/* overlay */
+struct nv50_disp_overlay_channel_dma_v0 {
+ __u8 version;
+ __u8 pad01[2];
+ __u8 head;
+ __u32 pushbuf;
+};
+
+#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
+
+/* overlay immediate */
+struct nv50_disp_overlay_v0 {
+ __u8 version;
+ __u8 head;
+ __u8 pad02[6];
+};
+
+#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
+
+/*******************************************************************************
+ * fermi
+ ******************************************************************************/
+
+#define FERMI_A_ZBC_COLOR 0x00
+#define FERMI_A_ZBC_DEPTH 0x01
+#define FERMI_A_ZCULL_BIND 0x02
+#define FERMI_A_ZBC_QUERY_COLOR 0x03
+#define FERMI_A_ZBC_QUERY_DEPTH 0x04
+#define FERMI_A_ZBC_QUERY_TABLE_SIZE 0x05
+
+struct fermi_a_zbc_color_v0 {
+ __u8 version;
+#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
+#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
+#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
+#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
+#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
+#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
+#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
+#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
+#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
+#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
+#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
+#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
+#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
+#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
+#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
+#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
+#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
+#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
+#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
+ __u8 format;
+ __u8 index;
+ __u8 pad03[5];
+ __u32 ds[4];
+ __u32 l2[4];
+};
+
+struct fermi_a_zbc_query_v0 {
+ __u8 version;
+ __u8 pad03[3];
+ __u32 ds[4];
+ __u32 l2[4];
+ __u32 format;
+ __u32 index;
+ __u32 table_size;
+};
+
+struct fermi_a_zbc_depth_v0 {
+ __u8 version;
+#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
+ __u8 format;
+ __u8 index;
+ __u8 pad03[5];
+ __u32 ds;
+ __u32 l2;
+};
+
+struct fermi_a_zcull_bind_v0 {
+ __u8 version;
+ __u8 pad03[3];
+#define FERMI_A_ZCULL_BIND_MODE_GLOBAL 0x00
+#define FERMI_A_ZCULL_BIND_MODE_NO_CTXSW 0x01
+#define FERMI_A_ZCULL_BIND_MODE_SEPARATE_BUFFER 0x02
+ __u32 mode;
+ __u64 gpu_va;
+};
+
+#define KEPLER_SET_CHANNEL_PRIORITY 0x00
+#define KEPLER_SET_CHANNEL_TIMEOUT 0x01
+
+struct kepler_set_channel_priority_v0 {
+ __u8 version;
+#define KEPLER_SET_CHANNEL_PRIORITY_LOW 0x00
+#define KEPLER_SET_CHANNEL_PRIORITY_MEDIUM 0x01
+#define KEPLER_SET_CHANNEL_PRIORITY_HIGH 0x02
+ __u8 priority;
+ __u8 pad03[6];
+};
+
+struct kepler_set_channel_timeout_v0 {
+ __u8 version;
+ __u8 pad03[3];
+ __u32 timeout_ms;
+};
+
+#endif
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index d42105c..91d2f31 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -33,6 +33,14 @@
extern "C" {
#endif
+/* reserved object handles when using deprecated object APIs - these
+ * are here so that libdrm can allow interoperability with the new
+ * object APIs
+ */
+#define NOUVEAU_ABI16_CLIENT 0xffffffff
+#define NOUVEAU_ABI16_DEVICE 0xdddddddd
+#define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n))
+
struct drm_nouveau_channel_alloc {
uint32_t fb_ctxdma_handle;
uint32_t tt_ctxdma_handle;
@@ -121,6 +129,12 @@
__u32 tile_flags;
};
+struct drm_nouveau_gem_set_tiling {
+ uint32_t handle;
+ uint32_t tile_mode;
+ uint32_t tile_flags;
+};
+
struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info;
__u32 channel_hint;
@@ -179,6 +193,21 @@
__u64 gart_available;
};
+#define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001
+#define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002
+struct drm_nouveau_gem_pushbuf_2 {
+ uint32_t channel;
+ uint32_t flags;
+ uint32_t nr_push;
+ uint32_t nr_buffers;
+ int32_t fence; /* in/out, depends on flags */
+ uint32_t pad;
+ uint64_t push; /* in raw hw format */
+ uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */
+ uint64_t vram_available;
+ uint64_t gart_available;
+};
+
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
@@ -191,6 +220,19 @@
__u32 handle;
};
+#define NOUVEAU_GEM_AS_SPARSE 0x00000001
+struct drm_nouveau_gem_as_alloc {
+ uint64_t pages; /* in, page length */
+ uint32_t page_size; /* in, byte page size */
+ uint32_t flags; /* in, flags of address space */
+ uint64_t align; /* in, requested alignment in bytes */
+ uint64_t address; /* in/out, non-zero for fixed address allocation */
+};
+
+struct drm_nouveau_gem_as_free {
+ uint64_t address; /* in, byte address */
+};
+
enum nouveau_bus_type {
NV_AGP = 0,
NV_PCI = 1,
@@ -200,6 +242,34 @@
struct drm_nouveau_sarea {
};
+#define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8
+#define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13
+#define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31
+#define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32
+struct drm_nouveau_gem_set_error_notifier {
+ uint32_t channel;
+ uint32_t buffer;
+ uint32_t offset; /* in bytes, u32-aligned */
+};
+
+struct drm_nouveau_gem_map {
+ uint32_t handle;
+ uint32_t domain;
+ uint64_t offset;
+ uint64_t delta;
+ uint64_t length;
+ uint32_t tile_mode;
+ uint32_t tile_flags;
+};
+
+struct drm_nouveau_gem_unmap {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+ uint64_t delta;
+ uint64_t length;
+};
+
#define DRM_NOUVEAU_GETPARAM 0x00
#define DRM_NOUVEAU_SETPARAM 0x01
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
@@ -214,8 +284,17 @@
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
#define DRM_NOUVEAU_GEM_INFO 0x44
+/* The ioctls below are marked as staging */
+#define DRM_NOUVEAU_GEM_SET_TILING 0x50
+#define DRM_NOUVEAU_GEM_PUSHBUF_2 0x51
+#define DRM_NOUVEAU_GEM_SET_INFO 0x52
+#define DRM_NOUVEAU_GEM_AS_ALLOC 0x53
+#define DRM_NOUVEAU_GEM_AS_FREE 0x54
+#define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER 0x55
+#define DRM_NOUVEAU_GEM_MAP 0x56
+#define DRM_NOUVEAU_GEM_UNMAP 0x57
+
#if defined(__cplusplus)
}
#endif
-
#endif /* __NOUVEAU_DRM_H__ */
diff --git a/include/drm/nouveau_ioctl.h b/include/drm/nouveau_ioctl.h
new file mode 100644
index 0000000..4cd8e32
--- /dev/null
+++ b/include/drm/nouveau_ioctl.h
@@ -0,0 +1,128 @@
+#ifndef __NVIF_IOCTL_H__
+#define __NVIF_IOCTL_H__
+
+struct nvif_ioctl_v0 {
+ __u8 version;
+#define NVIF_IOCTL_V0_OWNER_NVIF 0x00
+#define NVIF_IOCTL_V0_OWNER_ANY 0xff
+ __u8 owner;
+#define NVIF_IOCTL_V0_NOP 0x00
+#define NVIF_IOCTL_V0_SCLASS 0x01
+#define NVIF_IOCTL_V0_NEW 0x02
+#define NVIF_IOCTL_V0_DEL 0x03
+#define NVIF_IOCTL_V0_MTHD 0x04
+#define NVIF_IOCTL_V0_RD 0x05
+#define NVIF_IOCTL_V0_WR 0x06
+#define NVIF_IOCTL_V0_MAP 0x07
+#define NVIF_IOCTL_V0_UNMAP 0x08
+#define NVIF_IOCTL_V0_NTFY_NEW 0x09
+#define NVIF_IOCTL_V0_NTFY_DEL 0x0a
+#define NVIF_IOCTL_V0_NTFY_GET 0x0b
+#define NVIF_IOCTL_V0_NTFY_PUT 0x0c
+ __u8 type;
+ __u8 path_nr;
+#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00
+#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff
+ __u8 pad04[3];
+ __u8 route;
+ __u64 token;
+ __u32 path[8]; /* in reverse */
+ __u8 data[]; /* ioctl data (below) */
+};
+
+struct nvif_ioctl_nop {
+};
+
+struct nvif_ioctl_sclass_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 count;
+ __u8 pad02[6];
+ __u32 oclass[];
+};
+
+struct nvif_ioctl_new_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 pad01[6];
+ __u8 route;
+ __u64 token;
+ __u32 handle;
+/* these class numbers are made up by us, and not nvidia-assigned */
+#define NVIF_IOCTL_NEW_V0_PERFCTR 0x0000ffff
+#define NVIF_IOCTL_NEW_V0_CONTROL 0x0000fffe
+ __u32 oclass;
+ __u8 data[]; /* class data (class.h) */
+};
+
+struct nvif_ioctl_del {
+};
+
+struct nvif_ioctl_rd_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 size;
+ __u8 pad02[2];
+ __u32 data;
+ __u64 addr;
+};
+
+struct nvif_ioctl_wr_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 size;
+ __u8 pad02[2];
+ __u32 data;
+ __u64 addr;
+};
+
+struct nvif_ioctl_map_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 pad01[3];
+ __u32 length;
+ __u64 handle;
+};
+
+struct nvif_ioctl_unmap {
+};
+
+struct nvif_ioctl_ntfy_new_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 event;
+ __u8 index;
+ __u8 pad03[5];
+ __u8 data[]; /* event request data (event.h) */
+};
+
+struct nvif_ioctl_ntfy_del_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 index;
+ __u8 pad02[6];
+};
+
+struct nvif_ioctl_ntfy_get_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 index;
+ __u8 pad02[6];
+};
+
+struct nvif_ioctl_ntfy_put_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 index;
+ __u8 pad02[6];
+};
+
+struct nvif_ioctl_mthd_v0 {
+ /* nvif_ioctl ... */
+ __u8 version;
+ __u8 method;
+ __u8 pad02[6];
+ __u8 data[]; /* method data (class.h) */
+};
+
+#endif
diff --git a/include/drm/qxl_drm.h b/include/drm/qxl_drm.h
index 880999d..38a0dbd 100644
--- a/include/drm/qxl_drm.h
+++ b/include/drm/qxl_drm.h
@@ -24,6 +24,7 @@
#ifndef QXL_DRM_H
#define QXL_DRM_H
+#include <stddef.h>
#include "drm.h"
#if defined(__cplusplus)
@@ -88,6 +89,7 @@
__u32 pad;
};
+/* XXX: call it drm_qxl_commands? */
struct drm_qxl_execbuffer {
__u32 flags; /* for future use */
__u32 commands_num;
diff --git a/include/drm/tegra_drm.h b/include/drm/tegra_drm.h
index 6c07919..f01f7a1 100644
--- a/include/drm/tegra_drm.h
+++ b/include/drm/tegra_drm.h
@@ -32,618 +32,175 @@
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
-/**
- * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
- */
struct drm_tegra_gem_create {
- /**
- * @size:
- *
- * The size, in bytes, of the buffer object to be created.
- */
__u64 size;
-
- /**
- * @flags:
- *
- * A bitmask of flags that influence the creation of GEM objects:
- *
- * DRM_TEGRA_GEM_CREATE_TILED
- * Use the 16x16 tiling format for this buffer.
- *
- * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
- * The buffer has a bottom-up layout.
- */
__u32 flags;
-
- /**
- * @handle:
- *
- * The handle of the created GEM object. Set by the kernel upon
- * successful completion of the IOCTL.
- */
__u32 handle;
};
-/**
- * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
- */
struct drm_tegra_gem_mmap {
- /**
- * @handle:
- *
- * Handle of the GEM object to obtain an mmap offset for.
- */
__u32 handle;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
-
- /**
- * @offset:
- *
- * The mmap offset for the given GEM object. Set by the kernel upon
- * successful completion of the IOCTL.
- */
__u64 offset;
};
-/**
- * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
- */
struct drm_tegra_syncpt_read {
- /**
- * @id:
- *
- * ID of the syncpoint to read the current value from.
- */
__u32 id;
-
- /**
- * @value:
- *
- * The current syncpoint value. Set by the kernel upon successful
- * completion of the IOCTL.
- */
__u32 value;
};
-/**
- * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
- */
struct drm_tegra_syncpt_incr {
- /**
- * @id:
- *
- * ID of the syncpoint to increment.
- */
__u32 id;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
};
-/**
- * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
- */
struct drm_tegra_syncpt_wait {
- /**
- * @id:
- *
- * ID of the syncpoint to wait on.
- */
__u32 id;
-
- /**
- * @thresh:
- *
- * Threshold value for which to wait.
- */
__u32 thresh;
-
- /**
- * @timeout:
- *
- * Timeout, in milliseconds, to wait.
- */
__u32 timeout;
-
- /**
- * @value:
- *
- * The new syncpoint value after the wait. Set by the kernel upon
- * successful completion of the IOCTL.
- */
__u32 value;
};
#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
-/**
- * struct drm_tegra_open_channel - parameters for the open channel IOCTL
- */
struct drm_tegra_open_channel {
- /**
- * @client:
- *
- * The client ID for this channel.
- */
__u32 client;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
-
- /**
- * @context:
- *
- * The application context of this channel. Set by the kernel upon
- * successful completion of the IOCTL. This context needs to be passed
- * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
- */
__u64 context;
};
-/**
- * struct drm_tegra_close_channel - parameters for the close channel IOCTL
- */
struct drm_tegra_close_channel {
- /**
- * @context:
- *
- * The application context of this channel. This is obtained from the
- * DRM_TEGRA_OPEN_CHANNEL IOCTL.
- */
__u64 context;
};
-/**
- * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
- */
struct drm_tegra_get_syncpt {
- /**
- * @context:
- *
- * The application context identifying the channel for which to obtain
- * the syncpoint ID.
- */
__u64 context;
-
- /**
- * @index:
- *
- * Index of the client syncpoint for which to obtain the ID.
- */
__u32 index;
-
- /**
- * @id:
- *
- * The ID of the given syncpoint. Set by the kernel upon successful
- * completion of the IOCTL.
- */
__u32 id;
};
-/**
- * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
- */
struct drm_tegra_get_syncpt_base {
- /**
- * @context:
- *
- * The application context identifying for which channel to obtain the
- * wait base.
- */
__u64 context;
-
- /**
- * @syncpt:
- *
- * ID of the syncpoint for which to obtain the wait base.
- */
__u32 syncpt;
-
- /**
- * @id:
- *
- * The ID of the wait base corresponding to the client syncpoint. Set
- * by the kernel upon successful completion of the IOCTL.
- */
__u32 id;
};
-/**
- * struct drm_tegra_syncpt - syncpoint increment operation
- */
struct drm_tegra_syncpt {
- /**
- * @id:
- *
- * ID of the syncpoint to operate on.
- */
__u32 id;
-
- /**
- * @incrs:
- *
- * Number of increments to perform for the syncpoint.
- */
__u32 incrs;
};
-/**
- * struct drm_tegra_cmdbuf - structure describing a command buffer
- */
struct drm_tegra_cmdbuf {
- /**
- * @handle:
- *
- * Handle to a GEM object containing the command buffer.
- */
__u32 handle;
-
- /**
- * @offset:
- *
- * Offset, in bytes, into the GEM object identified by @handle at
- * which the command buffer starts.
- */
__u32 offset;
-
- /**
- * @words:
- *
- * Number of 32-bit words in this command buffer.
- */
__u32 words;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
};
-/**
- * struct drm_tegra_reloc - GEM object relocation structure
- */
struct drm_tegra_reloc {
struct {
- /**
- * @cmdbuf.handle:
- *
- * Handle to the GEM object containing the command buffer for
- * which to perform this GEM object relocation.
- */
__u32 handle;
-
- /**
- * @cmdbuf.offset:
- *
- * Offset, in bytes, into the command buffer at which to
- * insert the relocated address.
- */
__u32 offset;
} cmdbuf;
struct {
- /**
- * @target.handle:
- *
- * Handle to the GEM object to be relocated.
- */
__u32 handle;
-
- /**
- * @target.offset:
- *
- * Offset, in bytes, into the target GEM object at which the
- * relocated data starts.
- */
__u32 offset;
} target;
-
- /**
- * @shift:
- *
- * The number of bits by which to shift relocated addresses.
- */
__u32 shift;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
};
-/**
- * struct drm_tegra_waitchk - wait check structure
- */
struct drm_tegra_waitchk {
- /**
- * @handle:
- *
- * Handle to the GEM object containing a command stream on which to
- * perform the wait check.
- */
__u32 handle;
-
- /**
- * @offset:
- *
- * Offset, in bytes, of the location in the command stream to perform
- * the wait check on.
- */
__u32 offset;
-
- /**
- * @syncpt:
- *
- * ID of the syncpoint to wait check.
- */
__u32 syncpt;
-
- /**
- * @thresh:
- *
- * Threshold value for which to check.
- */
__u32 thresh;
};
-/**
- * struct drm_tegra_submit - job submission structure
- */
struct drm_tegra_submit {
- /**
- * @context:
- *
- * The application context identifying the channel to use for the
- * execution of this job.
- */
__u64 context;
-
- /**
- * @num_syncpts:
- *
- * The number of syncpoints operated on by this job. This defines the
- * length of the array pointed to by @syncpts.
- */
__u32 num_syncpts;
-
- /**
- * @num_cmdbufs:
- *
- * The number of command buffers to execute as part of this job. This
- * defines the length of the array pointed to by @cmdbufs.
- */
__u32 num_cmdbufs;
-
- /**
- * @num_relocs:
- *
- * The number of relocations to perform before executing this job.
- * This defines the length of the array pointed to by @relocs.
- */
__u32 num_relocs;
-
- /**
- * @num_waitchks:
- *
- * The number of wait checks to perform as part of this job. This
- * defines the length of the array pointed to by @waitchks.
- */
__u32 num_waitchks;
-
- /**
- * @waitchk_mask:
- *
- * Bitmask of valid wait checks.
- */
__u32 waitchk_mask;
-
- /**
- * @timeout:
- *
- * Timeout, in milliseconds, before this job is cancelled.
- */
__u32 timeout;
-
- /**
- * @syncpts:
- *
- * A pointer to an array of &struct drm_tegra_syncpt structures that
- * specify the syncpoint operations performed as part of this job.
- * The number of elements in the array must be equal to the value
- * given by @num_syncpts.
- */
+ __u32 pad;
__u64 syncpts;
-
- /**
- * @cmdbufs:
- *
- * A pointer to an array of &struct drm_tegra_cmdbuf structures that
- * define the command buffers to execute as part of this job. The
- * number of elements in the array must be equal to the value given
- * by @num_syncpts.
- */
__u64 cmdbufs;
-
- /**
- * @relocs:
- *
- * A pointer to an array of &struct drm_tegra_reloc structures that
- * specify the relocations that need to be performed before executing
- * this job. The number of elements in the array must be equal to the
- * value given by @num_relocs.
- */
__u64 relocs;
-
- /**
- * @waitchks:
- *
- * A pointer to an array of &struct drm_tegra_waitchk structures that
- * specify the wait checks to be performed while executing this job.
- * The number of elements in the array must be equal to the value
- * given by @num_waitchks.
- */
__u64 waitchks;
+ __u32 fence; /* Return value */
- /**
- * @fence:
- *
- * The threshold of the syncpoint associated with this job after it
- * has been completed. Set by the kernel upon successful completion of
- * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
- * wait for this job to be finished.
- */
- __u32 fence;
-
- /**
- * @reserved:
- *
- * This field is reserved for future use. Must be 0.
- */
- __u32 reserved[5];
+ __u32 reserved[5]; /* future expansion */
};
#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
-/**
- * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
- */
struct drm_tegra_gem_set_tiling {
- /**
- * @handle:
- *
- * Handle to the GEM object for which to set the tiling parameters.
- */
+ /* input */
__u32 handle;
-
- /**
- * @mode:
- *
- * The tiling mode to set. Must be one of:
- *
- * DRM_TEGRA_GEM_TILING_MODE_PITCH
- * pitch linear format
- *
- * DRM_TEGRA_GEM_TILING_MODE_TILED
- * 16x16 tiling format
- *
- * DRM_TEGRA_GEM_TILING_MODE_BLOCK
- * 16Bx2 tiling format
- */
__u32 mode;
-
- /**
- * @value:
- *
- * The value to set for the tiling mode parameter.
- */
__u32 value;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
};
-/**
- * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
- */
struct drm_tegra_gem_get_tiling {
- /**
- * @handle:
- *
- * Handle to the GEM object for which to query the tiling parameters.
- */
+ /* input */
__u32 handle;
-
- /**
- * @mode:
- *
- * The tiling mode currently associated with the GEM object. Set by
- * the kernel upon successful completion of the IOCTL.
- */
+ /* output */
__u32 mode;
-
- /**
- * @value:
- *
- * The tiling mode parameter currently associated with the GEM object.
- * Set by the kernel upon successful completion of the IOCTL.
- */
__u32 value;
-
- /**
- * @pad:
- *
- * Structure padding that may be used in the future. Must be 0.
- */
__u32 pad;
};
#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
-/**
- * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
- */
struct drm_tegra_gem_set_flags {
- /**
- * @handle:
- *
- * Handle to the GEM object for which to set the flags.
- */
+ /* input */
__u32 handle;
-
- /**
- * @flags:
- *
- * The flags to set for the GEM object.
- */
+ /* output */
__u32 flags;
};
-/**
- * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
- */
struct drm_tegra_gem_get_flags {
- /**
- * @handle:
- *
- * Handle to the GEM object for which to query the flags.
- */
+ /* input */
__u32 handle;
-
- /**
- * @flags:
- *
- * The flags currently associated with the GEM object. Set by the
- * kernel upon successful completion of the IOCTL.
- */
+ /* output */
__u32 flags;
};
+enum request_type {
+ DRM_TEGRA_REQ_TYPE_CLK_KHZ = 0,
+ DRM_TEGRA_REQ_TYPE_BW_KBPS,
+};
+
+struct drm_tegra_get_clk_rate {
+ /* class ID*/
+ __u32 id;
+ /* request type: KBps or KHz */
+ __u32 type;
+ /* numeric value for type */
+ __u64 data;
+};
+
+struct drm_tegra_set_clk_rate {
+ /* class ID*/
+ __u32 id;
+ /* request type: KBps or KHz */
+ __u32 type;
+ /* numeric value for type */
+ __u64 data;
+};
+
+struct drm_tegra_keepon {
+ /* channel context (from opening a channel) */
+ __u64 context;
+};
+
#define DRM_TEGRA_GEM_CREATE 0x00
#define DRM_TEGRA_GEM_MMAP 0x01
#define DRM_TEGRA_SYNCPT_READ 0x02
@@ -658,6 +215,10 @@
#define DRM_TEGRA_GEM_GET_TILING 0x0b
#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
+#define DRM_TEGRA_GET_CLK_RATE 0x0e
+#define DRM_TEGRA_SET_CLK_RATE 0x0f
+#define DRM_TEGRA_START_KEEPON 0x10
+#define DRM_TEGRA_STOP_KEEPON 0x11
#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
@@ -665,7 +226,7 @@
#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
-#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
+#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
@@ -673,6 +234,10 @@
#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
+#define DRM_IOCTL_TEGRA_GET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_RATE, struct drm_tegra_get_clk_rate)
+#define DRM_IOCTL_TEGRA_SET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_RATE, struct drm_tegra_set_clk_rate)
+#define DRM_IOCTL_TEGRA_START_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_START_KEEPON, struct drm_tegra_keepon)
+#define DRM_IOCTL_TEGRA_STOP_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_STOP_KEEPON, struct drm_tegra_keepon)
#if defined(__cplusplus)
}
diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h
index 31f50de..4117117 100644
--- a/include/drm/vc4_drm.h
+++ b/include/drm/vc4_drm.h
@@ -183,17 +183,10 @@
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
- /* Syncobj handle to wait on. If set, processing of this render job
- * will not start until the syncobj is signaled. 0 means ignore.
+ /* Unused field to align this struct on 64 bits. Must be set to 0.
+ * If one ever needs to add an u32 field to this struct, this field
+ * can be used.
*/
- __u32 in_sync;
-
- /* Syncobj handle to export fence to. If set, the fence in the syncobj
- * will be replaced with a fence that signals upon completion of this
- * render job. 0 means ignore.
- */
- __u32 out_sync;
-
__u32 pad2;
};
diff --git a/include/drm/virtgpu_drm.h b/include/drm/virtgpu_drm.h
index f06a789..9a781f0 100644
--- a/include/drm/virtgpu_drm.h
+++ b/include/drm/virtgpu_drm.h
@@ -47,13 +47,6 @@
#define DRM_VIRTGPU_WAIT 0x08
#define DRM_VIRTGPU_GET_CAPS 0x09
-#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
-#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
-#define VIRTGPU_EXECBUF_FLAGS (\
- VIRTGPU_EXECBUF_FENCE_FD_IN |\
- VIRTGPU_EXECBUF_FENCE_FD_OUT |\
- 0)
-
struct drm_virtgpu_map {
__u64 offset; /* use for mmap system call */
__u32 handle;
@@ -61,12 +54,12 @@
};
struct drm_virtgpu_execbuffer {
- __u32 flags;
+ __u32 flags; /* for future use */
__u32 size;
__u64 command; /* void* */
__u64 bo_handles;
__u32 num_bo_handles;
- __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
+ __u32 pad;
};
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
@@ -144,7 +137,7 @@
DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
+ DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
struct drm_virtgpu_execbuffer)
#define DRM_IOCTL_VIRTGPU_GETPARAM \
diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h
index 2b8d47e..0bc784f 100644
--- a/include/drm/vmwgfx_drm.h
+++ b/include/drm/vmwgfx_drm.h
@@ -361,7 +361,7 @@
* Allocate a DMA buffer that is visible also to the host.
* NOTE: The buffer is
* identified by a handle and an offset, which are private to the guest, but
- * usable in the command stream. The guest kernel may translate these
+ * useable in the command stream. The guest kernel may translate these
* and patch up the command stream accordingly. In the future, the offset may
* be zero at all times, or it may disappear from the interface before it is
* fixed.
@@ -446,7 +446,7 @@
*
* This IOCTL controls the overlay units of the svga device.
* The SVGA overlay units does not work like regular hardware units in
- * that they do not automatically read back the contents of the given dma
+ * that they do not automaticaly read back the contents of the given dma
* buffer. But instead only read back for each call to this ioctl, and
* at any point between this call being made and a following call that
* either changes the buffer or disables the stream.
@@ -1035,7 +1035,7 @@
* for read-only.
* @drm_vmw_synccpu_write: Sync for write. Block all command submissions
* referencing this buffer.
- * @drm_vmw_synccpu_dontblock: Don't wait for GPU idle, but rather return
+ * @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return
* -EBUSY should the buffer be busy.
* @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer
* while the buffer is synced for CPU. This is similar to the GEM bo idle
diff --git a/intel/Android.sources.bp b/intel/Android.sources.bp
index 46e0328..459c070 100644
--- a/intel/Android.sources.bp
+++ b/intel/Android.sources.bp
@@ -7,7 +7,6 @@
"intel_bufmgr_fake.c",
"intel_bufmgr_gem.c",
"intel_decode.c",
- "intel_chipset.c",
"mm.c",
],
}
diff --git a/intel/Makefile.am b/intel/Makefile.am
index bad44f5..c52e8c0 100644
--- a/intel/Makefile.am
+++ b/intel/Makefile.am
@@ -26,7 +26,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
$(PCIACCESS_CFLAGS) \
@@ -57,7 +56,6 @@
tests/gen7-2d-copy.batch \
tests/gen7-3d.batch
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = \
$(BATCHES:.batch=.batch.sh) \
intel-symbol-check
diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index aa27e27..6947ab7 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -1,12 +1,10 @@
LIBDRM_INTEL_FILES := \
- i915_pciids.h \
intel_bufmgr.c \
intel_bufmgr_priv.h \
intel_bufmgr_fake.c \
intel_bufmgr_gem.c \
intel_decode.c \
intel_chipset.h \
- intel_chipset.c \
mm.c \
mm.h \
uthash.h
diff --git a/intel/i915_pciids.h b/intel/i915_pciids.h
deleted file mode 100644
index c7cdbfc..0000000
--- a/intel/i915_pciids.h
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * Copyright 2013 Intel Corporation
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-#ifndef _I915_PCIIDS_H
-#define _I915_PCIIDS_H
-
-/*
- * A pci_device_id struct {
- * __u32 vendor, device;
- * __u32 subvendor, subdevice;
- * __u32 class, class_mask;
- * kernel_ulong_t driver_data;
- * };
- * Don't use C99 here because "class" is reserved and we want to
- * give userspace flexibility.
- */
-#define INTEL_VGA_DEVICE(id, info) { \
- 0x8086, id, \
- ~0, ~0, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_QUANTA_VGA_DEVICE(info) { \
- 0x8086, 0x16a, \
- 0x152d, 0x8990, \
- 0x030000, 0xff0000, \
- (unsigned long) info }
-
-#define INTEL_I810_IDS(info) \
- INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \
- INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \
- INTEL_VGA_DEVICE(0x7125, info) /* I810_E */
-
-#define INTEL_I815_IDS(info) \
- INTEL_VGA_DEVICE(0x1132, info) /* I815*/
-
-#define INTEL_I830_IDS(info) \
- INTEL_VGA_DEVICE(0x3577, info)
-
-#define INTEL_I845G_IDS(info) \
- INTEL_VGA_DEVICE(0x2562, info)
-
-#define INTEL_I85X_IDS(info) \
- INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
- INTEL_VGA_DEVICE(0x358e, info)
-
-#define INTEL_I865G_IDS(info) \
- INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
-
-#define INTEL_I915G_IDS(info) \
- INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
- INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
-
-#define INTEL_I915GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
-
-#define INTEL_I945G_IDS(info) \
- INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
-
-#define INTEL_I945GM_IDS(info) \
- INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
- INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
-
-#define INTEL_I965G_IDS(info) \
- INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
- INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
- INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
- INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
-
-#define INTEL_G33_IDS(info) \
- INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
- INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
- INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
-
-#define INTEL_I965GM_IDS(info) \
- INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
- INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
-
-#define INTEL_GM45_IDS(info) \
- INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
-
-#define INTEL_G45_IDS(info) \
- INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
- INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
- INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
- INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
- INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
- INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-
-#define INTEL_PINEVIEW_IDS(info) \
- INTEL_VGA_DEVICE(0xa001, info), \
- INTEL_VGA_DEVICE(0xa011, info)
-
-#define INTEL_IRONLAKE_D_IDS(info) \
- INTEL_VGA_DEVICE(0x0042, info)
-
-#define INTEL_IRONLAKE_M_IDS(info) \
- INTEL_VGA_DEVICE(0x0046, info)
-
-#define INTEL_SNB_D_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0102, info), \
- INTEL_VGA_DEVICE(0x010A, info)
-
-#define INTEL_SNB_D_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0112, info), \
- INTEL_VGA_DEVICE(0x0122, info)
-
-#define INTEL_SNB_D_IDS(info) \
- INTEL_SNB_D_GT1_IDS(info), \
- INTEL_SNB_D_GT2_IDS(info)
-
-#define INTEL_SNB_M_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0106, info)
-
-#define INTEL_SNB_M_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0116, info), \
- INTEL_VGA_DEVICE(0x0126, info)
-
-#define INTEL_SNB_M_IDS(info) \
- INTEL_SNB_M_GT1_IDS(info), \
- INTEL_SNB_M_GT2_IDS(info)
-
-#define INTEL_IVB_M_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
-
-#define INTEL_IVB_M_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
-
-#define INTEL_IVB_M_IDS(info) \
- INTEL_IVB_M_GT1_IDS(info), \
- INTEL_IVB_M_GT2_IDS(info)
-
-#define INTEL_IVB_D_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */
-
-#define INTEL_IVB_D_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
-
-#define INTEL_IVB_D_IDS(info) \
- INTEL_IVB_D_GT1_IDS(info), \
- INTEL_IVB_D_GT2_IDS(info)
-
-#define INTEL_IVB_Q_IDS(info) \
- INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
-
-#define INTEL_HSW_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
- INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
- INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
- INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
- INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
- INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
- INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
- INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
- INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
-
-#define INTEL_HSW_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
- INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
- INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
- INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
- INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
- INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
- INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
- INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
- INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
- INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
-
-#define INTEL_HSW_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
- INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
- INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
- INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
- INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
- INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
- INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
- INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
- INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
- INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
-
-#define INTEL_HSW_IDS(info) \
- INTEL_HSW_GT1_IDS(info), \
- INTEL_HSW_GT2_IDS(info), \
- INTEL_HSW_GT3_IDS(info)
-
-#define INTEL_VLV_IDS(info) \
- INTEL_VGA_DEVICE(0x0f30, info), \
- INTEL_VGA_DEVICE(0x0f31, info), \
- INTEL_VGA_DEVICE(0x0f32, info), \
- INTEL_VGA_DEVICE(0x0f33, info), \
- INTEL_VGA_DEVICE(0x0157, info), \
- INTEL_VGA_DEVICE(0x0155, info)
-
-#define INTEL_BDW_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
- INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
- INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
- INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
- INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
- INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */
-
-#define INTEL_BDW_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
- INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
- INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \
- INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
- INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
-
-#define INTEL_BDW_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x162E, info), /* ULX */\
- INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
- INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
-
-#define INTEL_BDW_RSVD_IDS(info) \
- INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
- INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
- INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \
- INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
- INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
-
-#define INTEL_BDW_IDS(info) \
- INTEL_BDW_GT1_IDS(info), \
- INTEL_BDW_GT2_IDS(info), \
- INTEL_BDW_GT3_IDS(info), \
- INTEL_BDW_RSVD_IDS(info)
-
-#define INTEL_CHV_IDS(info) \
- INTEL_VGA_DEVICE(0x22b0, info), \
- INTEL_VGA_DEVICE(0x22b1, info), \
- INTEL_VGA_DEVICE(0x22b2, info), \
- INTEL_VGA_DEVICE(0x22b3, info)
-
-#define INTEL_SKL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
- INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
- INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
-
-#define INTEL_SKL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
- INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
- INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
-
-#define INTEL_SKL_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
- INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */
-
-#define INTEL_SKL_GT4_IDS(info) \
- INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
- INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
- INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
- INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \
- INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */
-
-#define INTEL_SKL_IDS(info) \
- INTEL_SKL_GT1_IDS(info), \
- INTEL_SKL_GT2_IDS(info), \
- INTEL_SKL_GT3_IDS(info), \
- INTEL_SKL_GT4_IDS(info)
-
-#define INTEL_BXT_IDS(info) \
- INTEL_VGA_DEVICE(0x0A84, info), \
- INTEL_VGA_DEVICE(0x1A84, info), \
- INTEL_VGA_DEVICE(0x1A85, info), \
- INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
- INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
-
-#define INTEL_GLK_IDS(info) \
- INTEL_VGA_DEVICE(0x3184, info), \
- INTEL_VGA_DEVICE(0x3185, info)
-
-#define INTEL_KBL_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
- INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
- INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
- INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
- INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
- INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
- INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
-
-#define INTEL_KBL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
- INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \
- INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
- INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
- INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
- INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
-
-#define INTEL_KBL_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
-
-#define INTEL_KBL_GT4_IDS(info) \
- INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
-
-/* AML/KBL Y GT2 */
-#define INTEL_AML_KBL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \
- INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */
-
-/* AML/CFL Y GT2 */
-#define INTEL_AML_CFL_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x87CA, info)
-
-/* CML GT1 */
-#define INTEL_CML_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x9B21, info), \
- INTEL_VGA_DEVICE(0x9BAA, info), \
- INTEL_VGA_DEVICE(0x9BAB, info), \
- INTEL_VGA_DEVICE(0x9BAC, info), \
- INTEL_VGA_DEVICE(0x9BA0, info), \
- INTEL_VGA_DEVICE(0x9BA5, info), \
- INTEL_VGA_DEVICE(0x9BA8, info), \
- INTEL_VGA_DEVICE(0x9BA4, info), \
- INTEL_VGA_DEVICE(0x9BA2, info)
-
-/* CML GT2 */
-#define INTEL_CML_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x9B41, info), \
- INTEL_VGA_DEVICE(0x9BCA, info), \
- INTEL_VGA_DEVICE(0x9BCB, info), \
- INTEL_VGA_DEVICE(0x9BCC, info), \
- INTEL_VGA_DEVICE(0x9BC0, info), \
- INTEL_VGA_DEVICE(0x9BC5, info), \
- INTEL_VGA_DEVICE(0x9BC8, info), \
- INTEL_VGA_DEVICE(0x9BC4, info), \
- INTEL_VGA_DEVICE(0x9BC2, info)
-
-#define INTEL_KBL_IDS(info) \
- INTEL_KBL_GT1_IDS(info), \
- INTEL_KBL_GT2_IDS(info), \
- INTEL_KBL_GT3_IDS(info), \
- INTEL_KBL_GT4_IDS(info), \
- INTEL_AML_KBL_GT2_IDS(info)
-
-/* CFL S */
-#define INTEL_CFL_S_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
- INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
- INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */
-
-#define INTEL_CFL_S_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \
- INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */
-
-/* CFL H */
-#define INTEL_CFL_H_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x3E9C, info)
-
-#define INTEL_CFL_H_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
- INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
-
-/* CFL U GT2 */
-#define INTEL_CFL_U_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA9, info)
-
-/* CFL U GT3 */
-#define INTEL_CFL_U_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
- INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
-
-/* WHL/CFL U GT1 */
-#define INTEL_WHL_U_GT1_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA1, info), \
- INTEL_VGA_DEVICE(0x3EA4, info)
-
-/* WHL/CFL U GT2 */
-#define INTEL_WHL_U_GT2_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA0, info), \
- INTEL_VGA_DEVICE(0x3EA3, info)
-
-/* WHL/CFL U GT3 */
-#define INTEL_WHL_U_GT3_IDS(info) \
- INTEL_VGA_DEVICE(0x3EA2, info)
-
-#define INTEL_CFL_IDS(info) \
- INTEL_CFL_S_GT1_IDS(info), \
- INTEL_CFL_S_GT2_IDS(info), \
- INTEL_CFL_H_GT1_IDS(info), \
- INTEL_CFL_H_GT2_IDS(info), \
- INTEL_CFL_U_GT2_IDS(info), \
- INTEL_CFL_U_GT3_IDS(info), \
- INTEL_WHL_U_GT1_IDS(info), \
- INTEL_WHL_U_GT2_IDS(info), \
- INTEL_WHL_U_GT3_IDS(info), \
- INTEL_AML_CFL_GT2_IDS(info), \
- INTEL_CML_GT1_IDS(info), \
- INTEL_CML_GT2_IDS(info)
-
-/* CNL */
-#define INTEL_CNL_IDS(info) \
- INTEL_VGA_DEVICE(0x5A51, info), \
- INTEL_VGA_DEVICE(0x5A59, info), \
- INTEL_VGA_DEVICE(0x5A41, info), \
- INTEL_VGA_DEVICE(0x5A49, info), \
- INTEL_VGA_DEVICE(0x5A52, info), \
- INTEL_VGA_DEVICE(0x5A5A, info), \
- INTEL_VGA_DEVICE(0x5A42, info), \
- INTEL_VGA_DEVICE(0x5A4A, info), \
- INTEL_VGA_DEVICE(0x5A50, info), \
- INTEL_VGA_DEVICE(0x5A40, info), \
- INTEL_VGA_DEVICE(0x5A54, info), \
- INTEL_VGA_DEVICE(0x5A5C, info), \
- INTEL_VGA_DEVICE(0x5A44, info), \
- INTEL_VGA_DEVICE(0x5A4C, info)
-
-/* ICL */
-#define INTEL_ICL_11_IDS(info) \
- INTEL_VGA_DEVICE(0x8A50, info), \
- INTEL_VGA_DEVICE(0x8A51, info), \
- INTEL_VGA_DEVICE(0x8A5C, info), \
- INTEL_VGA_DEVICE(0x8A5D, info), \
- INTEL_VGA_DEVICE(0x8A59, info), \
- INTEL_VGA_DEVICE(0x8A58, info), \
- INTEL_VGA_DEVICE(0x8A52, info), \
- INTEL_VGA_DEVICE(0x8A5A, info), \
- INTEL_VGA_DEVICE(0x8A5B, info), \
- INTEL_VGA_DEVICE(0x8A57, info), \
- INTEL_VGA_DEVICE(0x8A56, info), \
- INTEL_VGA_DEVICE(0x8A71, info), \
- INTEL_VGA_DEVICE(0x8A70, info), \
- INTEL_VGA_DEVICE(0x8A53, info)
-
-/* EHL */
-#define INTEL_EHL_IDS(info) \
- INTEL_VGA_DEVICE(0x4500, info), \
- INTEL_VGA_DEVICE(0x4571, info), \
- INTEL_VGA_DEVICE(0x4551, info), \
- INTEL_VGA_DEVICE(0x4541, info)
-
-#endif /* _I915_PCIIDS_H */
diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check
index de377be..4d30a4b 100755
--- a/intel/intel-symbol-check
+++ b/intel/intel-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_INTEL_H_FILES
diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c
index 68d97c0..192de09 100644
--- a/intel/intel_bufmgr.c
+++ b/intel/intel_bufmgr.c
@@ -45,21 +45,21 @@
* Convenience functions for buffer management methods.
*/
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
unsigned long size, unsigned int alignment)
{
return bufmgr->bo_alloc(bufmgr, name, size, alignment);
}
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
unsigned long size, unsigned int alignment)
{
return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
}
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
const char *name, void *addr,
uint32_t tiling_mode,
@@ -73,7 +73,7 @@
return NULL;
}
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
int x, int y, int cpp, uint32_t *tiling_mode,
unsigned long *pitch, unsigned long flags)
@@ -82,13 +82,13 @@
tiling_mode, pitch, flags);
}
-drm_public void
+void
drm_intel_bo_reference(drm_intel_bo *bo)
{
bo->bufmgr->bo_reference(bo);
}
-drm_public void
+void
drm_intel_bo_unreference(drm_intel_bo *bo)
{
if (bo == NULL)
@@ -97,26 +97,26 @@
bo->bufmgr->bo_unreference(bo);
}
-drm_public int
+int
drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
{
return buf->bufmgr->bo_map(buf, write_enable);
}
-drm_public int
+int
drm_intel_bo_unmap(drm_intel_bo *buf)
{
return buf->bufmgr->bo_unmap(buf);
}
-drm_public int
+int
drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
unsigned long size, const void *data)
{
return bo->bufmgr->bo_subdata(bo, offset, size, data);
}
-drm_public int
+int
drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
unsigned long size, void *data)
{
@@ -135,26 +135,26 @@
return 0;
}
-drm_public void
+void
drm_intel_bo_wait_rendering(drm_intel_bo *bo)
{
bo->bufmgr->bo_wait_rendering(bo);
}
-drm_public void
+void
drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
{
bufmgr->destroy(bufmgr);
}
-drm_public int
+int
drm_intel_bo_exec(drm_intel_bo *bo, int used,
drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
{
return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
}
-drm_public int
+int
drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
unsigned int rings)
@@ -174,19 +174,19 @@
}
}
-drm_public void
+void
drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
{
bufmgr->debug = enable_debug;
}
-drm_public int
+int
drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
{
return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
}
-drm_public int
+int
drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
{
if (bo->bufmgr->bo_flink)
@@ -195,7 +195,7 @@
return -ENODEV;
}
-drm_public int
+int
drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
drm_intel_bo *target_bo, uint32_t target_offset,
uint32_t read_domains, uint32_t write_domain)
@@ -206,7 +206,7 @@
}
/* For fence registers, not GL fences */
-drm_public int
+int
drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
drm_intel_bo *target_bo, uint32_t target_offset,
uint32_t read_domains, uint32_t write_domain)
@@ -217,7 +217,7 @@
}
-drm_public int
+int
drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
{
if (bo->bufmgr->bo_pin)
@@ -226,7 +226,7 @@
return -ENODEV;
}
-drm_public int
+int
drm_intel_bo_unpin(drm_intel_bo *bo)
{
if (bo->bufmgr->bo_unpin)
@@ -235,7 +235,7 @@
return -ENODEV;
}
-drm_public int
+int
drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
uint32_t stride)
{
@@ -246,7 +246,7 @@
return 0;
}
-drm_public int
+int
drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
uint32_t * swizzle_mode)
{
@@ -258,7 +258,7 @@
return 0;
}
-drm_public int
+int
drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
{
if (bo->bufmgr->bo_set_softpin_offset)
@@ -267,7 +267,7 @@
return -ENODEV;
}
-drm_public int
+int
drm_intel_bo_disable_reuse(drm_intel_bo *bo)
{
if (bo->bufmgr->bo_disable_reuse)
@@ -275,7 +275,7 @@
return 0;
}
-drm_public int
+int
drm_intel_bo_is_reusable(drm_intel_bo *bo)
{
if (bo->bufmgr->bo_is_reusable)
@@ -283,7 +283,7 @@
return 0;
}
-drm_public int
+int
drm_intel_bo_busy(drm_intel_bo *bo)
{
if (bo->bufmgr->bo_busy)
@@ -291,7 +291,7 @@
return 0;
}
-drm_public int
+int
drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
{
if (bo->bufmgr->bo_madvise)
@@ -299,7 +299,7 @@
return -1;
}
-drm_public int
+int
drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
{
if (bo->bufmgr->bo_use_48b_address_range) {
@@ -310,13 +310,13 @@
return -ENODEV;
}
-drm_public int
+int
drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
{
return bo->bufmgr->bo_references(bo, target_bo);
}
-drm_public int
+int
drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
{
if (bufmgr->get_pipe_from_crtc_id)
@@ -360,7 +360,7 @@
}
#endif
-drm_public int
+int
drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
{
diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c
index 0cec51f..3b24b81 100644
--- a/intel/intel_bufmgr_fake.c
+++ b/intel/intel_bufmgr_fake.c
@@ -241,7 +241,7 @@
return 0;
}
-drm_public void
+void
drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
unsigned int (*emit) (void *priv),
void (*wait) (unsigned int fence,
@@ -764,7 +764,7 @@
* -- just evict everything
* -- and wait for idle
*/
-drm_public void
+void
drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
@@ -860,7 +860,7 @@
4096);
}
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
const char *name,
unsigned long offset,
@@ -955,7 +955,7 @@
* Set the buffer as not requiring backing store, and instead get the callback
* invoked whenever it would be set dirty.
*/
-drm_public void
+void
drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
void (*invalidate_cb) (drm_intel_bo *bo,
void *ptr),
@@ -1409,7 +1409,7 @@
bo_fake->write_domain = 0;
}
-drm_public void
+void
drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
int (*exec) (drm_intel_bo *bo,
unsigned int used,
@@ -1532,7 +1532,7 @@
* Used by the X Server on LeaveVT, when the card memory is no longer our
* own.
*/
-drm_public void
+void
drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr;
@@ -1567,7 +1567,7 @@
pthread_mutex_unlock(&bufmgr_fake->lock);
}
-drm_public void
+void
drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
volatile unsigned int
*last_dispatch)
@@ -1577,7 +1577,7 @@
bufmgr_fake->last_dispatch = (volatile int *)last_dispatch;
}
-drm_public drm_intel_bufmgr *
+drm_intel_bufmgr *
drm_intel_bufmgr_fake_init(int fd, unsigned long low_offset,
void *low_virtual, unsigned long size,
volatile unsigned int *last_dispatch)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index fbf4873..5c47a46 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1075,7 +1075,7 @@
* This can be used when one application needs to pass a buffer object
* to another.
*/
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
const char *name,
unsigned int handle)
@@ -1562,7 +1562,7 @@
return 0;
}
-drm_public int
+int
drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -1621,7 +1621,7 @@
* undefined).
*/
-drm_public int
+int
drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -1710,7 +1710,7 @@
return ret;
}
-drm_public int
+int
drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
{
return drm_intel_gem_bo_unmap(bo);
@@ -1835,7 +1835,7 @@
* Note that some kernels have broken the inifite wait for negative values
* promise, upgrade to latest stable kernels if this is the case.
*/
-drm_public int
+int
drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -1871,7 +1871,7 @@
* In combination with drm_intel_gem_bo_pin() and manual fence management, we
* can do tiled pixmaps this way.
*/
-drm_public void
+void
drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -2098,7 +2098,7 @@
read_domains, write_domain, true);
}
-drm_public int
+int
drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
{
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -2121,7 +2121,7 @@
*
* This also removes all softpinned targets being referenced by the BO.
*/
-drm_public void
+void
drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -2277,7 +2277,7 @@
}
}
-drm_public void
+void
drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
int x1, int y1, int width, int height,
enum aub_dump_bmp_format format,
@@ -2479,14 +2479,14 @@
-1, NULL, flags);
}
-drm_public int
+int
drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
int used, unsigned int flags)
{
return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
}
-drm_public int
+int
drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
drm_intel_context *ctx,
int used,
@@ -2627,7 +2627,7 @@
return 0;
}
-drm_public drm_intel_bo *
+drm_intel_bo *
drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, int prime_fd, int size)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
@@ -2710,7 +2710,7 @@
return NULL;
}
-drm_public int
+int
drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
@@ -2762,7 +2762,7 @@
* size is only bounded by how many buffers of that size we've managed to have
* in flight at once.
*/
-drm_public void
+void
drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
@@ -2784,7 +2784,7 @@
* which can be checked using drm_intel_bufmgr_can_disable_implicit_sync,
* or subsequent execbufs involving the bo will generate EINVAL.
*/
-drm_public void
+void
drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo)
{
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -2803,7 +2803,7 @@
* function can be used to restore the implicit sync before subsequent
* rendering.
*/
-drm_public void
+void
drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo)
{
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -2815,7 +2815,7 @@
* Query whether the kernel supports disabling of its implicit synchronisation
* before execbuf. See drm_intel_gem_bo_disable_implicit_sync()
*/
-drm_public int
+int
drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
@@ -2830,7 +2830,7 @@
* allocation. If this option is not enabled, all relocs will have fence
* register allocated.
*/
-drm_public void
+void
drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
@@ -3109,7 +3109,7 @@
}
}
-drm_public void
+void
drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
@@ -3178,7 +3178,7 @@
return devid;
}
-drm_public int
+int
drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
@@ -3192,7 +3192,7 @@
* This function has to be called before drm_intel_bufmgr_gem_set_aub_dump()
* for it to have any effect.
*/
-drm_public void
+void
drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
const char *filename)
{
@@ -3206,7 +3206,7 @@
* You can set up a GTT and upload your objects into the referenced
* space, then send off batchbuffers and get BMPs out the other end.
*/
-drm_public void
+void
drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
{
fprintf(stderr, "libdrm aub dumping is deprecated.\n\n"
@@ -3216,7 +3216,7 @@
"See the intel_aubdump man page for more details.\n");
}
-drm_public drm_intel_context *
+drm_intel_context *
drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
@@ -3243,7 +3243,7 @@
return context;
}
-drm_public int
+int
drm_intel_gem_context_get_id(drm_intel_context *ctx, uint32_t *ctx_id)
{
if (ctx == NULL)
@@ -3254,7 +3254,7 @@
return 0;
}
-drm_public void
+void
drm_intel_gem_context_destroy(drm_intel_context *ctx)
{
drm_intel_bufmgr_gem *bufmgr_gem;
@@ -3277,7 +3277,7 @@
free(ctx);
}
-drm_public int
+int
drm_intel_get_reset_stats(drm_intel_context *ctx,
uint32_t *reset_count,
uint32_t *active,
@@ -3311,7 +3311,7 @@
return ret;
}
-drm_public int
+int
drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
uint32_t offset,
uint64_t *result)
@@ -3329,7 +3329,7 @@
return ret;
}
-drm_public int
+int
drm_intel_get_subslice_total(int fd, unsigned int *subslice_total)
{
drm_i915_getparam_t gp;
@@ -3345,7 +3345,7 @@
return 0;
}
-drm_public int
+int
drm_intel_get_eu_total(int fd, unsigned int *eu_total)
{
drm_i915_getparam_t gp;
@@ -3361,7 +3361,7 @@
return 0;
}
-drm_public int
+int
drm_intel_get_pooled_eu(int fd)
{
drm_i915_getparam_t gp;
@@ -3376,7 +3376,7 @@
return ret;
}
-drm_public int
+int
drm_intel_get_min_eu_in_pool(int fd)
{
drm_i915_getparam_t gp;
@@ -3412,7 +3412,8 @@
* default state (no annotations), call this function with a \c count
* of zero.
*/
-drm_public void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
+void
+drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
drm_intel_aub_annotation *annotations,
unsigned count)
{
@@ -3453,7 +3454,7 @@
}
}
-drm_public void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo)
+void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -3501,7 +3502,7 @@
return bo_gem->gtt_virtual;
}
-drm_public void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo)
+void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -3545,7 +3546,7 @@
return bo_gem->mem_virtual;
}
-drm_public void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo)
+void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
@@ -3594,7 +3595,7 @@
*
* \param fd File descriptor of the opened DRM device.
*/
-drm_public drm_intel_bufmgr *
+drm_intel_bufmgr *
drm_intel_bufmgr_gem_init(int fd, int batch_size)
{
drm_intel_bufmgr_gem *bufmgr_gem;
@@ -3655,7 +3656,11 @@
bufmgr_gem->gen = 7;
else if (IS_GEN8(bufmgr_gem->pci_device))
bufmgr_gem->gen = 8;
- else if (!intel_get_genx(bufmgr_gem->pci_device, &bufmgr_gem->gen)) {
+ else if (IS_GEN9(bufmgr_gem->pci_device))
+ bufmgr_gem->gen = 9;
+ else if (IS_GEN10(bufmgr_gem->pci_device))
+ bufmgr_gem->gen = 10;
+ else {
free(bufmgr_gem);
bufmgr_gem = NULL;
goto exit;
diff --git a/intel/intel_bufmgr_priv.h b/intel/intel_bufmgr_priv.h
index baaf4bb..7e360a0 100644
--- a/intel/intel_bufmgr_priv.h
+++ b/intel/intel_bufmgr_priv.h
@@ -156,7 +156,7 @@
* address range (2^48).
*
* Any resource used with flat/heapless (0x00000000-0xfffff000)
- * General State Heap (GSH) or Instructions State Heap (ISH) must
+ * General State Heap (GSH) or Intructions State Heap (ISH) must
* be in a 32-bit range. 48-bit range will only be used when explicitly
* requested.
*
diff --git a/intel/intel_chipset.c b/intel/intel_chipset.c
deleted file mode 100644
index 5aa4a2f..0000000
--- a/intel/intel_chipset.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2018 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-#include "intel_chipset.h"
-
-#include <inttypes.h>
-#include <stdbool.h>
-
-#include "i915_pciids.h"
-
-#undef INTEL_VGA_DEVICE
-#define INTEL_VGA_DEVICE(id, gen) { id, gen }
-
-static const struct pci_device {
- uint16_t device;
- uint16_t gen;
-} pciids[] = {
- /* Keep ids sorted by gen; latest gen first */
- INTEL_ICL_11_IDS(11),
- INTEL_CNL_IDS(10),
- INTEL_CFL_IDS(9),
- INTEL_GLK_IDS(9),
- INTEL_KBL_IDS(9),
- INTEL_BXT_IDS(9),
- INTEL_SKL_IDS(9),
-};
-
-drm_private bool intel_is_genx(unsigned int devid, int gen)
-{
- const struct pci_device *p,
- *pend = pciids + sizeof(pciids) / sizeof(pciids[0]);
-
- for (p = pciids; p < pend; p++) {
- /* PCI IDs are sorted */
- if (p->gen < gen)
- break;
-
- if (p->device != devid)
- continue;
-
- if (gen == p->gen)
- return true;
-
- break;
- }
-
- return false;
-}
-
-drm_private bool intel_get_genx(unsigned int devid, int *gen)
-{
- const struct pci_device *p,
- *pend = pciids + sizeof(pciids) / sizeof(pciids[0]);
-
- for (p = pciids; p < pend; p++) {
- if (p->device != devid)
- continue;
-
- if (gen)
- *gen = p->gen;
-
- return true;
- }
-
- return false;
-}
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 5db207c..01d250e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -165,8 +165,96 @@
#define PCI_CHIP_CHERRYVIEW_2 0x22b2
#define PCI_CHIP_CHERRYVIEW_3 0x22b3
+#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
+#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
+#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
+#define PCI_CHIP_SKYLAKE_H_GT1 0x190B
+#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
+#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */
+#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */
+#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
+#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */
+#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */
+#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
+#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
+#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
+#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */
+#define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923
+#define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926
+#define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927
+#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
+#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
+#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D
+#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
+#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
+#define PCI_CHIP_SKYLAKE_H_GT4 0x193B
+#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
+
+#define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916
+#define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913
+#define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906
+#define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923
+#define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926
+#define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927
+#define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921
+#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
+#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
+#define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E
#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
+#define PCI_CHIP_KABYLAKE_M_GT2 0x5917
+#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
+#define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B
+#define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B
+#define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908
+#define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B
+#define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A
+#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
+#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
+
+#define PCI_CHIP_BROXTON_0 0x0A84
+#define PCI_CHIP_BROXTON_1 0x1A84
+#define PCI_CHIP_BROXTON_2 0x5A84
+#define PCI_CHIP_BROXTON_3 0x1A85
+#define PCI_CHIP_BROXTON_4 0x5A85
+
+#define PCI_CHIP_GLK 0x3184
+#define PCI_CHIP_GLK_2X6 0x3185
+
+#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
+#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
+#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99
+#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
+#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
+#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
+#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
+#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
+#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
+#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
+#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
+#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
+
+#define PCI_CHIP_CANNONLAKE_0 0x5A51
+#define PCI_CHIP_CANNONLAKE_1 0x5A59
+#define PCI_CHIP_CANNONLAKE_2 0x5A41
+#define PCI_CHIP_CANNONLAKE_3 0x5A49
+#define PCI_CHIP_CANNONLAKE_4 0x5A52
+#define PCI_CHIP_CANNONLAKE_5 0x5A5A
+#define PCI_CHIP_CANNONLAKE_6 0x5A42
+#define PCI_CHIP_CANNONLAKE_7 0x5A4A
+#define PCI_CHIP_CANNONLAKE_8 0x5A50
+#define PCI_CHIP_CANNONLAKE_9 0x5A40
+#define PCI_CHIP_CANNONLAKE_10 0x5A54
+#define PCI_CHIP_CANNONLAKE_11 0x5A5C
+#define PCI_CHIP_CANNONLAKE_12 0x5A44
+#define PCI_CHIP_CANNONLAKE_13 0x5A4C
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -327,16 +415,126 @@
#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
IS_CHERRYVIEW(devid))
-/* New platforms use kernel pci ids */
-#include <stdbool.h>
-#include <libdrm_macros.h>
+#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
-drm_private bool intel_is_genx(unsigned int devid, int gen);
-drm_private bool intel_get_genx(unsigned int devid, int *gen);
+#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
+ (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
-#define IS_GEN9(devid) intel_is_genx(devid, 9)
-#define IS_GEN10(devid) intel_is_genx(devid, 10)
-#define IS_GEN11(devid) intel_is_genx(devid, 11)
+#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \
+ (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \
+ (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
+
+#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \
+ (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
+ (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
+ (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
+ (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
+
+#define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \
+ (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \
+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
+
+#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
+ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
+
+#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
+ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
+
+#define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
+
+#define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
+ IS_KBL_GT2(devid) || \
+ IS_KBL_GT3(devid) || \
+ IS_KBL_GT4(devid))
+
+#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
+ IS_SKL_GT2(devid) || \
+ IS_SKL_GT3(devid) || \
+ IS_SKL_GT4(devid))
+
+#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
+ (devid) == PCI_CHIP_BROXTON_1 || \
+ (devid) == PCI_CHIP_BROXTON_2 || \
+ (devid) == PCI_CHIP_BROXTON_3 || \
+ (devid) == PCI_CHIP_BROXTON_4)
+
+#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
+ (devid) == PCI_CHIP_GLK_2X6)
+
+#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4)
+
+#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
+
+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
+ IS_CFL_H(devid) || \
+ IS_CFL_U(devid))
+
+#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
+ IS_BROXTON(devid) || \
+ IS_KABYLAKE(devid) || \
+ IS_GEMINILAKE(devid) || \
+ IS_COFFEELAKE(devid))
+
+#define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \
+ (devid) == PCI_CHIP_CANNONLAKE_1 || \
+ (devid) == PCI_CHIP_CANNONLAKE_2 || \
+ (devid) == PCI_CHIP_CANNONLAKE_3 || \
+ (devid) == PCI_CHIP_CANNONLAKE_4 || \
+ (devid) == PCI_CHIP_CANNONLAKE_5 || \
+ (devid) == PCI_CHIP_CANNONLAKE_6 || \
+ (devid) == PCI_CHIP_CANNONLAKE_7 || \
+ (devid) == PCI_CHIP_CANNONLAKE_8 || \
+ (devid) == PCI_CHIP_CANNONLAKE_9 || \
+ (devid) == PCI_CHIP_CANNONLAKE_10 || \
+ (devid) == PCI_CHIP_CANNONLAKE_11 || \
+ (devid) == PCI_CHIP_CANNONLAKE_12 || \
+ (devid) == PCI_CHIP_CANNONLAKE_13)
+
+#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
@@ -344,6 +542,7 @@
IS_GEN6(dev) || \
IS_GEN7(dev) || \
IS_GEN8(dev) || \
- intel_get_genx(dev, NULL))
+ IS_GEN9(dev) || \
+ IS_GEN10(dev))
#endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index e0a5166..bc7b04b 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3811,7 +3811,7 @@
return 1;
}
-drm_public struct drm_intel_decode *
+struct drm_intel_decode *
drm_intel_decode_context_alloc(uint32_t devid)
{
struct drm_intel_decode *ctx;
@@ -3823,8 +3823,10 @@
ctx->devid = devid;
ctx->out = stdout;
- if (intel_get_genx(devid, &ctx->gen))
- ;
+ if (IS_GEN10(devid))
+ ctx->gen = 10;
+ else if (IS_GEN9(devid))
+ ctx->gen = 9;
else if (IS_GEN8(devid))
ctx->gen = 8;
else if (IS_GEN7(devid))
@@ -3845,20 +3847,20 @@
return ctx;
}
-drm_public void
+void
drm_intel_decode_context_free(struct drm_intel_decode *ctx)
{
free(ctx);
}
-drm_public void
+void
drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
int dump_past_end)
{
ctx->dump_past_end = !!dump_past_end;
}
-drm_public void
+void
drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
void *data, uint32_t hw_offset, int count)
{
@@ -3867,7 +3869,7 @@
ctx->base_count = count;
}
-drm_public void
+void
drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
uint32_t head, uint32_t tail)
{
@@ -3875,7 +3877,7 @@
ctx->tail = tail;
}
-drm_public void
+void
drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
FILE *output)
{
@@ -3889,7 +3891,7 @@
* \param count number of DWORDs to decode in the batch buffer
* \param hw_offset hardware address for the buffer
*/
-drm_public void
+void
drm_intel_decode(struct drm_intel_decode *ctx)
{
int ret;
diff --git a/intel/meson.build b/intel/meson.build
index 3d6bbac..53c7fce 100644
--- a/intel/meson.build
+++ b/intel/meson.build
@@ -23,14 +23,14 @@
[
files(
'intel_bufmgr.c', 'intel_bufmgr_fake.c', 'intel_bufmgr_gem.c',
- 'intel_decode.c', 'mm.c', 'intel_chipset.c',
+ 'intel_decode.c', 'mm.c',
),
config_file,
],
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pciaccess, dep_pthread_stubs, dep_rt, dep_valgrind, dep_atomic_ops],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
version : '1.0.0',
install : true,
)
@@ -59,7 +59,7 @@
files('test_decode.c'),
include_directories : [inc_root, inc_drm],
link_with : [libdrm, libdrm_intel],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
test(
diff --git a/intel/mm.h b/intel/mm.h
index be3d90d..1b0f84f 100644
--- a/intel/mm.h
+++ b/intel/mm.h
@@ -73,7 +73,7 @@
drm_private extern void mmDestroy(struct mem_block *mmInit);
/**
- * For debugging purpose.
+ * For debuging purpose.
*/
drm_private extern void mmDumpMemInfo(const struct mem_block *mmInit);
diff --git a/libdrm_macros.h b/libdrm_macros.h
index 0dca827..3134ae9 100644
--- a/libdrm_macros.h
+++ b/libdrm_macros.h
@@ -25,10 +25,8 @@
#if HAVE_VISIBILITY
# define drm_private __attribute__((visibility("hidden")))
-# define drm_public __attribute__((visibility("default")))
#else
# define drm_private
-# define drm_public
#endif
diff --git a/libkms/Makefile.am b/libkms/Makefile.am
index ff4c1b2..461fc35 100644
--- a/libkms/Makefile.am
+++ b/libkms/Makefile.am
@@ -2,7 +2,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)
@@ -40,6 +39,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libkms.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = kms-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/libkms/api.c b/libkms/api.c
index caca1a8..22dd32d 100644
--- a/libkms/api.c
+++ b/libkms/api.c
@@ -33,12 +33,12 @@
#include "libdrm_macros.h"
#include "internal.h"
-drm_public int kms_create(int fd, struct kms_driver **out)
+int kms_create(int fd, struct kms_driver **out)
{
return linux_create(fd, out);
}
-drm_public int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
+int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out)
{
switch (key) {
case KMS_BO_TYPE:
@@ -49,7 +49,7 @@
return kms->get_prop(kms, key, out);
}
-drm_public int kms_destroy(struct kms_driver **kms)
+int kms_destroy(struct kms_driver **kms)
{
if (!(*kms))
return 0;
@@ -59,7 +59,7 @@
return 0;
}
-drm_public int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out)
+int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out)
{
unsigned width = 0;
unsigned height = 0;
@@ -97,7 +97,7 @@
return kms->bo_create(kms, width, height, type, attr, out);
}
-drm_public int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
+int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out)
{
switch (key) {
case KMS_PITCH:
@@ -113,17 +113,17 @@
return 0;
}
-drm_public int kms_bo_map(struct kms_bo *bo, void **out)
+int kms_bo_map(struct kms_bo *bo, void **out)
{
return bo->kms->bo_map(bo, out);
}
-drm_public int kms_bo_unmap(struct kms_bo *bo)
+int kms_bo_unmap(struct kms_bo *bo)
{
return bo->kms->bo_unmap(bo);
}
-drm_public int kms_bo_destroy(struct kms_bo **bo)
+int kms_bo_destroy(struct kms_bo **bo)
{
int ret;
diff --git a/libkms/kms-symbol-check b/libkms/kms-symbol-check
index 30f444f..a5c2120 100755
--- a/libkms/kms-symbol-check
+++ b/libkms/kms-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBKMS_H_FILES
diff --git a/libkms/libkms.pc.in b/libkms/libkms.pc.in
index 7c60429..1421b3e 100644
--- a/libkms/libkms.pc.in
+++ b/libkms/libkms.pc.in
@@ -4,7 +4,7 @@
includedir=@includedir@
Name: libkms
-Description: Library that abstracts away the different mm interface for kernel drivers
+Description: Library that abstract aways the different mm interface for kernel drivers
Version: 1.0.0
Libs: -L${libdir} -lkms
Cflags: -I${includedir}/libkms
diff --git a/libkms/meson.build b/libkms/meson.build
index dc93160..86d1a4e 100644
--- a/libkms/meson.build
+++ b/libkms/meson.build
@@ -44,7 +44,7 @@
libkms = shared_library(
'kms',
[files_libkms, config_file],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : libkms_include,
link_with : libdrm,
version : '1.0.0',
diff --git a/man/drm.xml b/man/drm.xml
index dbb67ad..1f55966 100644
--- a/man/drm.xml
+++ b/man/drm.xml
@@ -49,7 +49,7 @@
applications.</para>
<para>In earlier days, the kernel framework was solely used to provide raw
- hardware access to privileged user-space processes which implement
+ hardware access to priviledged user-space processes which implement
all the hardware abstraction layers. But more and more tasks were
moved into the kernel. All these interfaces are based on
<citerefentry><refentrytitle>ioctl</refentrytitle><manvolnum>2</manvolnum></citerefentry>
@@ -64,7 +64,7 @@
<citerefentry><refentrytitle>open</refentrytitle><manvolnum>2</manvolnum></citerefentry>
and
<citerefentry><refentrytitle>close</refentrytitle><manvolnum>2</manvolnum></citerefentry>.
- However, it still depends on the graphics driver which interfaces are
+ However, it still depends on the grapics driver which interfaces are
available on these devices. If an interface is not available, the
syscalls will fail with <literal>EINVAL</literal>.</para>
diff --git a/meson.build b/meson.build
index e292554..961ee59 100644
--- a/meson.build
+++ b/meson.build
@@ -21,7 +21,7 @@
project(
'libdrm',
['c'],
- version : '2.4.99',
+ version : '2.4.91',
license : 'MIT',
meson_version : '>= 0.43',
default_options : ['buildtype=debugoptimized', 'c_std=gnu99'],
@@ -157,7 +157,7 @@
with_vc4 = _vc4 == 'true' or ['arm', 'aarch64'].contains(host_machine.cpu_family())
endif
-# XXX: Apparently only freebsd and dragonfly bsd actually need this (and
+# XXX: Aparently only freebsd and dragonfly bsd actually need this (and
# gnu/kfreebsd), not openbsd and netbsd
with_libkms = false
_libkms = get_option('libkms')
@@ -192,7 +192,7 @@
warn_c_args = []
foreach a : ['-Wall', '-Wextra', '-Wsign-compare', '-Werror=undef',
- '-Werror=implicit-function-declaration', '-Wpointer-arith',
+ '-Werror-implicit-function-declaration', '-Wpointer-arith',
'-Wwrite-strings', '-Wstrict-prototypes', '-Wmissing-prototypes',
'-Wmissing-declarations', '-Wnested-externs', '-Wpacked',
'-Wswitch-enum', '-Wmissing-format-attribute',
@@ -211,9 +211,6 @@
endif
endforeach
-# all c args:
-libdrm_c_args = warn_c_args + ['-fvisibility=hidden']
-
dep_pciaccess = dependency('pciaccess', version : '>= 0.10', required : with_intel)
dep_cunit = dependency('cunit', version : '>= 2.1', required : false)
@@ -289,7 +286,7 @@
),
config_file,
],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
dependencies : [dep_valgrind, dep_rt, dep_m],
include_directories : inc_drm,
version : '2.4.0',
@@ -306,11 +303,10 @@
'include/drm/drm.h', 'include/drm/drm_fourcc.h', 'include/drm/drm_mode.h',
'include/drm/drm_sarea.h', 'include/drm/i915_drm.h',
'include/drm/mach64_drm.h', 'include/drm/mga_drm.h',
- 'include/drm/msm_drm.h', 'include/drm/nouveau_drm.h',
- 'include/drm/qxl_drm.h', 'include/drm/r128_drm.h',
- 'include/drm/radeon_drm.h', 'include/drm/amdgpu_drm.h',
- 'include/drm/savage_drm.h', 'include/drm/sis_drm.h',
- 'include/drm/tegra_drm.h', 'include/drm/vc4_drm.h',
+ 'include/drm/nouveau_drm.h', 'include/drm/qxl_drm.h',
+ 'include/drm/r128_drm.h', 'include/drm/radeon_drm.h',
+ 'include/drm/amdgpu_drm.h', 'include/drm/savage_drm.h',
+ 'include/drm/sis_drm.h', 'include/drm/tegra_drm.h', 'include/drm/vc4_drm.h',
'include/drm/via_drm.h', 'include/drm/virtgpu_drm.h',
subdir : 'libdrm',
)
diff --git a/nouveau/Makefile.am b/nouveau/Makefile.am
index 5574fd8..344a844 100644
--- a/nouveau/Makefile.am
+++ b/nouveau/Makefile.am
@@ -2,7 +2,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm \
@@ -30,6 +29,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_nouveau.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = nouveau-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/nouveau/bufctx.c b/nouveau/bufctx.c
index 00924b3..67b7570 100644
--- a/nouveau/bufctx.c
+++ b/nouveau/bufctx.c
@@ -58,7 +58,7 @@
return (struct nouveau_bufctx_priv *)bctx;
}
-drm_public int
+int
nouveau_bufctx_new(struct nouveau_client *client, int bins,
struct nouveau_bufctx **pbctx)
{
@@ -78,7 +78,7 @@
return -ENOMEM;
}
-drm_public void
+void
nouveau_bufctx_del(struct nouveau_bufctx **pbctx)
{
struct nouveau_bufctx_priv *pctx = nouveau_bufctx(*pbctx);
@@ -95,7 +95,7 @@
}
}
-drm_public void
+void
nouveau_bufctx_reset(struct nouveau_bufctx *bctx, int bin)
{
struct nouveau_bufctx_priv *pctx = nouveau_bufctx(bctx);
@@ -113,7 +113,7 @@
pbin->relocs = 0;
}
-drm_public struct nouveau_bufref *
+struct nouveau_bufref *
nouveau_bufctx_refn(struct nouveau_bufctx *bctx, int bin,
struct nouveau_bo *bo, uint32_t flags)
{
@@ -140,7 +140,7 @@
return &pref->base;
}
-drm_public struct nouveau_bufref *
+struct nouveau_bufref *
nouveau_bufctx_mthd(struct nouveau_bufctx *bctx, int bin, uint32_t packet,
struct nouveau_bo *bo, uint64_t data, uint32_t flags,
uint32_t vor, uint32_t tor)
diff --git a/nouveau/meson.build b/nouveau/meson.build
index 0c1498d..51c9a71 100644
--- a/nouveau/meson.build
+++ b/nouveau/meson.build
@@ -22,7 +22,7 @@
libdrm_nouveau = shared_library(
'drm_nouveau',
[files( 'nouveau.c', 'pushbuf.c', 'bufctx.c', 'abi16.c'), config_file],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_threads, dep_atomic_ops],
diff --git a/nouveau/nouveau-symbol-check b/nouveau/nouveau-symbol-check
index 6296244..b3a2410 100755
--- a/nouveau/nouveau-symbol-check
+++ b/nouveau/nouveau-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_NOUVEAU_H_FILES
diff --git a/nouveau/nouveau.c b/nouveau/nouveau.c
index f18d142..5559351 100644
--- a/nouveau/nouveau.c
+++ b/nouveau/nouveau.c
@@ -88,7 +88,7 @@
return drmCommandWriteRead(drm->fd, DRM_NOUVEAU_NVIF, args, argc);
}
-drm_public int
+int
nouveau_object_mthd(struct nouveau_object *obj,
uint32_t mthd, void *data, uint32_t size)
{
@@ -123,14 +123,14 @@
return ret;
}
-drm_public void
+void
nouveau_object_sclass_put(struct nouveau_sclass **psclass)
{
free(*psclass);
*psclass = NULL;
}
-drm_public int
+int
nouveau_object_sclass_get(struct nouveau_object *obj,
struct nouveau_sclass **psclass)
{
@@ -180,7 +180,7 @@
return ret;
}
-drm_public int
+int
nouveau_object_mclass(struct nouveau_object *obj,
const struct nouveau_mclass *mclass)
{
@@ -282,7 +282,7 @@
return 0;
}
-drm_public int
+int
nouveau_object_new(struct nouveau_object *parent, uint64_t handle,
uint32_t oclass, void *data, uint32_t length,
struct nouveau_object **pobj)
@@ -303,7 +303,7 @@
return 0;
}
-drm_public void
+void
nouveau_object_del(struct nouveau_object **pobj)
{
struct nouveau_object *obj = *pobj;
@@ -314,14 +314,14 @@
}
}
-drm_public void
+void
nouveau_drm_del(struct nouveau_drm **pdrm)
{
free(*pdrm);
*pdrm = NULL;
}
-drm_public int
+int
nouveau_drm_new(int fd, struct nouveau_drm **pdrm)
{
struct nouveau_drm *drm;
@@ -353,14 +353,14 @@
* is kept here to prevent AIGLX from crashing if the DDX is linked against
* the new libdrm, but the DRI driver against the old
*/
-drm_public int
+int
nouveau_device_open_existing(struct nouveau_device **pdev, int close, int fd,
drm_context_t ctx)
{
return -EACCES;
}
-drm_public int
+int
nouveau_device_new(struct nouveau_object *parent, int32_t oclass,
void *data, uint32_t size, struct nouveau_device **pdev)
{
@@ -454,7 +454,7 @@
return ret;
}
-drm_public int
+int
nouveau_device_wrap(int fd, int close, struct nouveau_device **pdev)
{
struct nouveau_drm *drm;
@@ -482,7 +482,7 @@
return 0;
}
-drm_public int
+int
nouveau_device_open(const char *busid, struct nouveau_device **pdev)
{
int ret = -ENODEV, fd = drmOpen("nouveau", busid);
@@ -494,7 +494,7 @@
return ret;
}
-drm_public void
+void
nouveau_device_del(struct nouveau_device **pdev)
{
struct nouveau_device_priv *nvdev = nouveau_device(*pdev);
@@ -513,7 +513,7 @@
}
}
-drm_public int
+int
nouveau_getparam(struct nouveau_device *dev, uint64_t param, uint64_t *value)
{
struct nouveau_drm *drm = nouveau_drm(&dev->object);
@@ -524,7 +524,7 @@
return ret;
}
-drm_public int
+int
nouveau_setparam(struct nouveau_device *dev, uint64_t param, uint64_t value)
{
struct nouveau_drm *drm = nouveau_drm(&dev->object);
@@ -532,7 +532,7 @@
return drmCommandWrite(drm->fd, DRM_NOUVEAU_SETPARAM, &r, sizeof(r));
}
-drm_public int
+int
nouveau_client_new(struct nouveau_device *dev, struct nouveau_client **pclient)
{
struct nouveau_device_priv *nvdev = nouveau_device(dev);
@@ -571,7 +571,7 @@
return ret;
}
-drm_public void
+void
nouveau_client_del(struct nouveau_client **pclient)
{
struct nouveau_client_priv *pcli = nouveau_client(*pclient);
@@ -618,7 +618,7 @@
free(nvbo);
}
-drm_public int
+int
nouveau_bo_new(struct nouveau_device *dev, uint32_t flags, uint32_t align,
uint64_t size, union nouveau_bo_config *config,
struct nouveau_bo **pbo)
@@ -709,7 +709,7 @@
}
}
-drm_public int
+int
nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle,
struct nouveau_bo **pbo)
{
@@ -721,7 +721,7 @@
return ret;
}
-drm_public int
+int
nouveau_bo_name_ref(struct nouveau_device *dev, uint32_t name,
struct nouveau_bo **pbo)
{
@@ -750,7 +750,7 @@
return ret;
}
-drm_public int
+int
nouveau_bo_name_get(struct nouveau_bo *bo, uint32_t *name)
{
struct drm_gem_flink req = { .handle = bo->handle };
@@ -772,7 +772,7 @@
return 0;
}
-drm_public void
+void
nouveau_bo_ref(struct nouveau_bo *bo, struct nouveau_bo **pref)
{
struct nouveau_bo *ref = *pref;
@@ -786,7 +786,7 @@
*pref = bo;
}
-drm_public int
+int
nouveau_bo_prime_handle_ref(struct nouveau_device *dev, int prime_fd,
struct nouveau_bo **bo)
{
@@ -806,7 +806,7 @@
return ret;
}
-drm_public int
+int
nouveau_bo_set_prime(struct nouveau_bo *bo, int *prime_fd)
{
struct nouveau_drm *drm = nouveau_drm(&bo->device->object);
@@ -821,7 +821,7 @@
return 0;
}
-drm_public int
+int
nouveau_bo_wait(struct nouveau_bo *bo, uint32_t access,
struct nouveau_client *client)
{
@@ -856,7 +856,7 @@
return ret;
}
-drm_public int
+int
nouveau_bo_map(struct nouveau_bo *bo, uint32_t access,
struct nouveau_client *client)
{
diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c
index e5f73f0..445c966 100644
--- a/nouveau/pushbuf.c
+++ b/nouveau/pushbuf.c
@@ -528,7 +528,7 @@
return ret;
}
-drm_public int
+int
nouveau_pushbuf_new(struct nouveau_client *client, struct nouveau_object *chan,
int nr, uint32_t size, bool immediate,
struct nouveau_pushbuf **ppush)
@@ -599,7 +599,7 @@
return 0;
}
-drm_public void
+void
nouveau_pushbuf_del(struct nouveau_pushbuf **ppush)
{
struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(*ppush);
@@ -625,7 +625,7 @@
*ppush = NULL;
}
-drm_public struct nouveau_bufctx *
+struct nouveau_bufctx *
nouveau_pushbuf_bufctx(struct nouveau_pushbuf *push, struct nouveau_bufctx *ctx)
{
struct nouveau_bufctx *prev = push->bufctx;
@@ -633,7 +633,7 @@
return prev;
}
-drm_public int
+int
nouveau_pushbuf_space(struct nouveau_pushbuf *push,
uint32_t dwords, uint32_t relocs, uint32_t pushes)
{
@@ -697,7 +697,7 @@
return flushed ? pushbuf_validate(push, false) : 0;
}
-drm_public void
+void
nouveau_pushbuf_data(struct nouveau_pushbuf *push, struct nouveau_bo *bo,
uint64_t offset, uint64_t length)
{
@@ -728,14 +728,14 @@
}
}
-drm_public int
+int
nouveau_pushbuf_refn(struct nouveau_pushbuf *push,
struct nouveau_pushbuf_refn *refs, int nr)
{
return pushbuf_refn(push, true, refs, nr);
}
-drm_public void
+void
nouveau_pushbuf_reloc(struct nouveau_pushbuf *push, struct nouveau_bo *bo,
uint32_t data, uint32_t flags, uint32_t vor, uint32_t tor)
{
@@ -743,13 +743,13 @@
push->cur++;
}
-drm_public int
+int
nouveau_pushbuf_validate(struct nouveau_pushbuf *push)
{
return pushbuf_validate(push, true);
}
-drm_public uint32_t
+uint32_t
nouveau_pushbuf_refd(struct nouveau_pushbuf *push, struct nouveau_bo *bo)
{
struct drm_nouveau_gem_pushbuf_bo *kref;
@@ -767,7 +767,7 @@
return flags;
}
-drm_public int
+int
nouveau_pushbuf_kick(struct nouveau_pushbuf *push, struct nouveau_object *chan)
{
if (!push->channel)
diff --git a/omap/Makefile.am b/omap/Makefile.am
index 38a1007..599bb9d 100644
--- a/omap/Makefile.am
+++ b/omap/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
@@ -21,6 +20,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_omap.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = omap-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/omap/meson.build b/omap/meson.build
index 54698c6..e57b8f5 100644
--- a/omap/meson.build
+++ b/omap/meson.build
@@ -22,7 +22,7 @@
'drm_omap',
[files('omap_drm.c'), config_file],
include_directories : [inc_root, inc_drm],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
link_with : libdrm,
dependencies : [dep_pthread_stubs, dep_atomic_ops],
version : '1.0.0',
diff --git a/omap/omap-symbol-check b/omap/omap-symbol-check
index 16da3c4..0fb4a0f 100755
--- a/omap/omap-symbol-check
+++ b/omap/omap-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.am/libdrm_omap*HEADERS
diff --git a/omap/omap_drm.c b/omap/omap_drm.c
index ffacea6..65275ec 100644
--- a/omap/omap_drm.c
+++ b/omap/omap_drm.c
@@ -88,7 +88,7 @@
return dev;
}
-drm_public struct omap_device * omap_device_new(int fd)
+struct omap_device * omap_device_new(int fd)
{
struct omap_device *dev = NULL;
@@ -111,13 +111,13 @@
return dev;
}
-drm_public struct omap_device * omap_device_ref(struct omap_device *dev)
+struct omap_device * omap_device_ref(struct omap_device *dev)
{
atomic_inc(&dev->refcnt);
return dev;
}
-drm_public void omap_device_del(struct omap_device *dev)
+void omap_device_del(struct omap_device *dev)
{
if (!atomic_dec_and_test(&dev->refcnt))
return;
@@ -128,7 +128,7 @@
free(dev);
}
-drm_public int
+int
omap_get_param(struct omap_device *dev, uint64_t param, uint64_t *value)
{
struct drm_omap_param req = {
@@ -146,7 +146,7 @@
return 0;
}
-drm_public int
+int
omap_set_param(struct omap_device *dev, uint64_t param, uint64_t value)
{
struct drm_omap_param req = {
@@ -226,7 +226,7 @@
/* allocate a new (un-tiled) buffer object */
-drm_public struct omap_bo *
+struct omap_bo *
omap_bo_new(struct omap_device *dev, uint32_t size, uint32_t flags)
{
union omap_gem_size gsize = {
@@ -239,7 +239,7 @@
}
/* allocate a new buffer object */
-drm_public struct omap_bo *
+struct omap_bo *
omap_bo_new_tiled(struct omap_device *dev, uint32_t width,
uint32_t height, uint32_t flags)
{
@@ -255,7 +255,7 @@
return omap_bo_new_impl(dev, gsize, flags);
}
-drm_public struct omap_bo *omap_bo_ref(struct omap_bo *bo)
+struct omap_bo *omap_bo_ref(struct omap_bo *bo)
{
atomic_inc(&bo->refcnt);
return bo;
@@ -281,7 +281,7 @@
}
/* import a buffer object from DRI2 name */
-drm_public struct omap_bo *
+struct omap_bo *
omap_bo_from_name(struct omap_device *dev, uint32_t name)
{
struct omap_bo *bo = NULL;
@@ -315,7 +315,7 @@
* fd so caller should close() the fd when it is otherwise done
* with it (even if it is still using the 'struct omap_bo *')
*/
-drm_public struct omap_bo *
+struct omap_bo *
omap_bo_from_dmabuf(struct omap_device *dev, int fd)
{
struct omap_bo *bo = NULL;
@@ -347,7 +347,7 @@
}
/* destroy a buffer object */
-drm_public void omap_bo_del(struct omap_bo *bo)
+void omap_bo_del(struct omap_bo *bo)
{
if (!bo) {
return;
@@ -380,7 +380,7 @@
}
/* get the global flink/DRI2 buffer name */
-drm_public int omap_bo_get_name(struct omap_bo *bo, uint32_t *name)
+int omap_bo_get_name(struct omap_bo *bo, uint32_t *name)
{
if (!bo->name) {
struct drm_gem_flink req = {
@@ -401,7 +401,7 @@
return 0;
}
-drm_public uint32_t omap_bo_handle(struct omap_bo *bo)
+uint32_t omap_bo_handle(struct omap_bo *bo)
{
return bo->handle;
}
@@ -409,7 +409,7 @@
/* caller owns the dmabuf fd that is returned and is responsible
* to close() it when done
*/
-drm_public int omap_bo_dmabuf(struct omap_bo *bo)
+int omap_bo_dmabuf(struct omap_bo *bo)
{
if (bo->fd < 0) {
struct drm_prime_handle req = {
@@ -428,7 +428,7 @@
return dup(bo->fd);
}
-drm_public uint32_t omap_bo_size(struct omap_bo *bo)
+uint32_t omap_bo_size(struct omap_bo *bo)
{
if (!bo->size) {
get_buffer_info(bo);
@@ -436,7 +436,7 @@
return bo->size;
}
-drm_public void *omap_bo_map(struct omap_bo *bo)
+void *omap_bo_map(struct omap_bo *bo)
{
if (!bo->map) {
if (!bo->offset) {
@@ -452,7 +452,7 @@
return bo->map;
}
-drm_public int omap_bo_cpu_prep(struct omap_bo *bo, enum omap_gem_op op)
+int omap_bo_cpu_prep(struct omap_bo *bo, enum omap_gem_op op)
{
struct drm_omap_gem_cpu_prep req = {
.handle = bo->handle,
@@ -462,7 +462,7 @@
DRM_OMAP_GEM_CPU_PREP, &req, sizeof(req));
}
-drm_public int omap_bo_cpu_fini(struct omap_bo *bo, enum omap_gem_op op)
+int omap_bo_cpu_fini(struct omap_bo *bo, enum omap_gem_op op)
{
struct drm_omap_gem_cpu_fini req = {
.handle = bo->handle,
diff --git a/radeon/Makefile.am b/radeon/Makefile.am
index e712a4a..e241531 100644
--- a/radeon/Makefile.am
+++ b/radeon/Makefile.am
@@ -26,7 +26,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
-I$(top_srcdir)/include/drm
@@ -44,6 +43,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_radeon.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = radeon-symbol-check
EXTRA_DIST = $(LIBDRM_RADEON_BOF_FILES) $(TESTS)
diff --git a/radeon/meson.build b/radeon/meson.build
index 1fc5282..b08c744 100644
--- a/radeon/meson.build
+++ b/radeon/meson.build
@@ -28,7 +28,7 @@
),
config_file,
],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs, dep_atomic_ops],
diff --git a/radeon/radeon-symbol-check b/radeon/radeon-symbol-check
index da605bb..7d79d90 100755
--- a/radeon/radeon-symbol-check
+++ b/radeon/radeon-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first five) are taken from the public headers.
# A list of the latter should be available Makefile.sources/LIBDRM_RADEON_H_FILES
diff --git a/radeon/radeon_bo.c b/radeon/radeon_bo.c
index 9192953..821807b 100644
--- a/radeon/radeon_bo.c
+++ b/radeon/radeon_bo.c
@@ -33,7 +33,7 @@
#include <radeon_bo.h>
#include <radeon_bo_int.h>
-drm_public void radeon_bo_debug(struct radeon_bo *bo, const char *op)
+void radeon_bo_debug(struct radeon_bo *bo, const char *op)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
@@ -41,7 +41,7 @@
op, bo, bo->handle, boi->size, boi->cref);
}
-drm_public struct radeon_bo *
+struct radeon_bo *
radeon_bo_open(struct radeon_bo_manager *bom, uint32_t handle, uint32_t size,
uint32_t alignment, uint32_t domains, uint32_t flags)
{
@@ -50,14 +50,14 @@
return bo;
}
-drm_public void radeon_bo_ref(struct radeon_bo *bo)
+void radeon_bo_ref(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
boi->cref++;
boi->bom->funcs->bo_ref(boi);
}
-drm_public struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo)
+struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
if (bo == NULL)
@@ -67,19 +67,19 @@
return boi->bom->funcs->bo_unref(boi);
}
-drm_public int radeon_bo_map(struct radeon_bo *bo, int write)
+int radeon_bo_map(struct radeon_bo *bo, int write)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
return boi->bom->funcs->bo_map(boi, write);
}
-drm_public int radeon_bo_unmap(struct radeon_bo *bo)
+int radeon_bo_unmap(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
return boi->bom->funcs->bo_unmap(boi);
}
-drm_public int radeon_bo_wait(struct radeon_bo *bo)
+int radeon_bo_wait(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
if (!boi->bom->funcs->bo_wait)
@@ -87,13 +87,13 @@
return boi->bom->funcs->bo_wait(boi);
}
-drm_public int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
+int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
return boi->bom->funcs->bo_is_busy(boi, domain);
}
-drm_public int
+int
radeon_bo_set_tiling(struct radeon_bo *bo,
uint32_t tiling_flags, uint32_t pitch)
{
@@ -101,7 +101,7 @@
return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch);
}
-drm_public int
+int
radeon_bo_get_tiling(struct radeon_bo *bo,
uint32_t *tiling_flags, uint32_t *pitch)
{
@@ -109,7 +109,7 @@
return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch);
}
-drm_public int radeon_bo_is_static(struct radeon_bo *bo)
+int radeon_bo_is_static(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
if (boi->bom->funcs->bo_is_static)
@@ -117,19 +117,19 @@
return 0;
}
-drm_public int
+int
radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, struct radeon_cs *cs)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
return boi->cref > 1;
}
-drm_public uint32_t radeon_bo_get_handle(struct radeon_bo *bo)
+uint32_t radeon_bo_get_handle(struct radeon_bo *bo)
{
return bo->handle;
}
-drm_public uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo)
+uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
uint32_t src_domain;
diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c
index 86f7c00..774b26e 100644
--- a/radeon/radeon_bo_gem.c
+++ b/radeon/radeon_bo_gem.c
@@ -281,7 +281,7 @@
.bo_is_referenced_by_cs = NULL,
};
-drm_public struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
+struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
{
struct bo_manager_gem *bomg;
@@ -294,7 +294,7 @@
return (struct radeon_bo_manager*)bomg;
}
-drm_public void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom)
+void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom)
{
struct bo_manager_gem *bomg = (struct bo_manager_gem*)bom;
@@ -304,21 +304,21 @@
free(bomg);
}
-drm_public uint32_t
+uint32_t
radeon_gem_name_bo(struct radeon_bo *bo)
{
struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
return bo_gem->name;
}
-drm_public void *
+void *
radeon_gem_get_reloc_in_cs(struct radeon_bo *bo)
{
struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
return &bo_gem->reloc_in_cs;
}
-drm_public int
+int
radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
{
struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
@@ -340,7 +340,7 @@
return 0;
}
-drm_public int
+int
radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
@@ -358,7 +358,7 @@
return r;
}
-drm_public int radeon_gem_prime_share_bo(struct radeon_bo *bo, int *handle)
+int radeon_gem_prime_share_bo(struct radeon_bo *bo, int *handle)
{
struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
int ret;
@@ -367,7 +367,7 @@
return ret;
}
-drm_public struct radeon_bo *
+struct radeon_bo *
radeon_gem_bo_open_prime(struct radeon_bo_manager *bom, int fd_handle, uint32_t size)
{
struct radeon_bo_gem *bo;
diff --git a/radeon/radeon_cs.c b/radeon/radeon_cs.c
index 1132d06..eb7859e 100644
--- a/radeon/radeon_cs.c
+++ b/radeon/radeon_cs.c
@@ -3,14 +3,14 @@
#include "radeon_cs.h"
#include "radeon_cs_int.h"
-drm_public struct radeon_cs *
+struct radeon_cs *
radeon_cs_create(struct radeon_cs_manager *csm, uint32_t ndw)
{
struct radeon_cs_int *csi = csm->funcs->cs_create(csm, ndw);
return (struct radeon_cs *)csi;
}
-drm_public int
+int
radeon_cs_write_reloc(struct radeon_cs *cs, struct radeon_bo *bo,
uint32_t read_domain, uint32_t write_domain,
uint32_t flags)
@@ -24,7 +24,7 @@
flags);
}
-drm_public int
+int
radeon_cs_begin(struct radeon_cs *cs, uint32_t ndw,
const char *file, const char *func, int line)
{
@@ -32,7 +32,7 @@
return csi->csm->funcs->cs_begin(csi, ndw, file, func, line);
}
-drm_public int
+int
radeon_cs_end(struct radeon_cs *cs,
const char *file, const char *func, int line)
{
@@ -40,37 +40,37 @@
return csi->csm->funcs->cs_end(csi, file, func, line);
}
-drm_public int radeon_cs_emit(struct radeon_cs *cs)
+int radeon_cs_emit(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return csi->csm->funcs->cs_emit(csi);
}
-drm_public int radeon_cs_destroy(struct radeon_cs *cs)
+int radeon_cs_destroy(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return csi->csm->funcs->cs_destroy(csi);
}
-drm_public int radeon_cs_erase(struct radeon_cs *cs)
+int radeon_cs_erase(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return csi->csm->funcs->cs_erase(csi);
}
-drm_public int radeon_cs_need_flush(struct radeon_cs *cs)
+int radeon_cs_need_flush(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return csi->csm->funcs->cs_need_flush(csi);
}
-drm_public void radeon_cs_print(struct radeon_cs *cs, FILE *file)
+void radeon_cs_print(struct radeon_cs *cs, FILE *file)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
csi->csm->funcs->cs_print(csi, file);
}
-drm_public void
+void
radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
@@ -80,7 +80,7 @@
csi->csm->gart_limit = limit;
}
-drm_public void radeon_cs_space_set_flush(struct radeon_cs *cs,
+void radeon_cs_space_set_flush(struct radeon_cs *cs,
void (*fn)(void *), void *data)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
@@ -88,7 +88,7 @@
csi->space_flush_data = data;
}
-drm_public uint32_t radeon_cs_get_id(struct radeon_cs *cs)
+uint32_t radeon_cs_get_id(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return csi->id;
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
index ef070c6..4d5fc13 100644
--- a/radeon/radeon_cs_gem.c
+++ b/radeon/radeon_cs_gem.c
@@ -536,7 +536,7 @@
return r;
}
-drm_public struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)
+struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)
{
struct radeon_cs_manager_gem *csm;
@@ -550,7 +550,7 @@
return &csm->base;
}
-drm_public void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm)
+void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm)
{
free(csm);
}
diff --git a/radeon/radeon_cs_space.c b/radeon/radeon_cs_space.c
index 039b041..8531c34 100644
--- a/radeon/radeon_cs_space.c
+++ b/radeon/radeon_cs_space.c
@@ -162,7 +162,7 @@
return RADEON_CS_SPACE_OK;
}
-drm_public void
+void
radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *bo,
uint32_t read_domains, uint32_t write_domain)
{
@@ -206,7 +206,7 @@
return 0;
}
-drm_public int
+int
radeon_cs_space_check_with_bo(struct radeon_cs *cs, struct radeon_bo *bo,
uint32_t read_domains, uint32_t write_domain)
{
@@ -227,13 +227,13 @@
return ret;
}
-drm_public int radeon_cs_space_check(struct radeon_cs *cs)
+int radeon_cs_space_check(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
return radeon_cs_check_space_internal(csi, NULL);
}
-drm_public void radeon_cs_space_reset_bos(struct radeon_cs *cs)
+void radeon_cs_space_reset_bos(struct radeon_cs *cs)
{
struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
int i;
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index ea0a27a..3cafcfc 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -2408,7 +2408,7 @@
/* ===========================================================================
* public API
*/
-drm_public struct radeon_surface_manager *
+struct radeon_surface_manager *
radeon_surface_manager_new(int fd)
{
struct radeon_surface_manager *surf_man;
@@ -2457,7 +2457,7 @@
return NULL;
}
-drm_public void
+void
radeon_surface_manager_free(struct radeon_surface_manager *surf_man)
{
free(surf_man);
@@ -2531,7 +2531,7 @@
return 0;
}
-drm_public int
+int
radeon_surface_init(struct radeon_surface_manager *surf_man,
struct radeon_surface *surf)
{
@@ -2548,7 +2548,7 @@
return surf_man->surface_init(surf_man, surf);
}
-drm_public int
+int
radeon_surface_best(struct radeon_surface_manager *surf_man,
struct radeon_surface *surf)
{
diff --git a/rockchip/Android.bp b/rockchip/Android.bp
new file mode 100644
index 0000000..daceacc
--- /dev/null
+++ b/rockchip/Android.bp
@@ -0,0 +1,13 @@
+cc_library_shared {
+ name: "libdrm_rockchip",
+ vendor: true,
+ shared_libs: ["libdrm"],
+
+ srcs: ["rockchip_drm.c"],
+
+ cflags: [
+ "-DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1",
+ "-Wall",
+ "-Werror",
+ ],
+}
diff --git a/rockchip/Makefile.am b/rockchip/Makefile.am
new file mode 100644
index 0000000..2ebb82f
--- /dev/null
+++ b/rockchip/Makefile.am
@@ -0,0 +1,20 @@
+AM_CFLAGS = \
+ $(WARN_CFLAGS) \
+ -I$(top_srcdir) \
+ -I$(top_srcdir)/rockchip \
+ $(PTHREADSTUBS_CFLAGS) \
+ -I$(top_srcdir)/include/drm
+
+libdrm_rockchip_la_LTLIBRARIES = libdrm_rockchip.la
+libdrm_rockchip_ladir = $(libdir)
+libdrm_rockchip_la_LDFLAGS = -version-number 1:0:0 -no-undefined
+libdrm_rockchip_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@
+
+libdrm_rockchip_la_SOURCES = \
+ rockchip_drm.c
+
+libdrm_rockchipincludedir = ${includedir}/libdrm
+libdrm_rockchipinclude_HEADERS = rockchip_drmif.h rockchip_drm.h
+
+pkgconfigdir = @pkgconfigdir@
+pkgconfig_DATA = libdrm_rockchip.pc
diff --git a/rockchip/libdrm_rockchip.pc.in b/rockchip/libdrm_rockchip.pc.in
new file mode 100644
index 0000000..13f22ac
--- /dev/null
+++ b/rockchip/libdrm_rockchip.pc.in
@@ -0,0 +1,11 @@
+prefix=@prefix@
+exec_prefix=@exec_prefix@
+libdir=@libdir@
+includedir=@includedir@
+
+Name: libdrm_rockchip
+Description: Userspace interface to rockchip kernel DRM services
+Version: 0.1
+Libs: -L${libdir} -ldrm_rockchip
+Cflags: -I${includedir} -I${includedir}/libdrm
+Requires.private: libdrm
diff --git a/rockchip/rockchip_drm.c b/rockchip/rockchip_drm.c
new file mode 100644
index 0000000..44a78be
--- /dev/null
+++ b/rockchip/rockchip_drm.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (C) ROCKCHIP, Inc.
+ * Author:yzq<yzq@rock-chips.com>
+ *
+ * based on exynos_drm.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+
+#include <sys/mman.h>
+#include <linux/stddef.h>
+
+#include <xf86drm.h>
+
+#include "rockchip_drm.h"
+#include "rockchip_drmif.h"
+
+/*
+ * Create rockchip drm device object.
+ *
+ * @fd: file descriptor to rockchip drm driver opened.
+ *
+ * if true, return the device object else NULL.
+ */
+struct rockchip_device *rockchip_device_create(int fd)
+{
+ struct rockchip_device *dev;
+
+ dev = calloc(1, sizeof(*dev));
+ if (!dev) {
+ fprintf(stderr, "failed to create device[%s].\n",
+ strerror(errno));
+ return NULL;
+ }
+
+ dev->fd = fd;
+
+ return dev;
+}
+
+/*
+ * Destroy rockchip drm device object
+ *
+ * @dev: rockchip drm device object.
+ */
+void rockchip_device_destroy(struct rockchip_device *dev)
+{
+ free(dev);
+}
+
+/*
+ * Create a rockchip buffer object to rockchip drm device.
+ *
+ * @dev: rockchip drm device object.
+ * @size: user-desired size.
+ * flags: user-desired memory type.
+ * user can set one or more types among several types to memory
+ * allocation and cache attribute types. and as default,
+ * ROCKCHIP_BO_NONCONTIG and ROCKCHIP-BO_NONCACHABLE types would
+ * be used.
+ *
+ * if true, return a rockchip buffer object else NULL.
+ */
+struct rockchip_bo *rockchip_bo_create(struct rockchip_device *dev,
+ size_t size, uint32_t flags)
+{
+ struct rockchip_bo *bo;
+ struct drm_rockchip_gem_create req = {
+ .size = size,
+ .flags = flags,
+ };
+
+ if (size == 0) {
+ fprintf(stderr, "invalid size.\n");
+ return NULL;
+ }
+
+ bo = calloc(1, sizeof(*bo));
+ if (!bo) {
+ fprintf(stderr, "failed to create bo[%s].\n",
+ strerror(errno));
+ goto fail;
+ }
+
+ bo->dev = dev;
+
+ if (drmIoctl(dev->fd, DRM_IOCTL_ROCKCHIP_GEM_CREATE, &req)){
+ fprintf(stderr, "failed to create gem object[%s].\n",
+ strerror(errno));
+ goto err_free_bo;
+ }
+
+ bo->handle = req.handle;
+ bo->size = size;
+ bo->flags = flags;
+
+ return bo;
+
+err_free_bo:
+ free(bo);
+fail:
+ return NULL;
+}
+
+struct rockchip_bo *rockchip_bo_from_handle(struct rockchip_device *dev,
+ uint32_t handle, uint32_t flags, uint32_t size)
+{
+ struct rockchip_bo *bo;
+
+ if (size == 0) {
+ fprintf(stderr, "invalid size.\n");
+ return NULL;
+ }
+
+ bo = calloc(1, sizeof(*bo));
+ if (!bo) {
+ fprintf(stderr, "failed to create bo[%s].\n",
+ strerror(errno));
+ return NULL;
+ }
+
+ bo->dev = dev;
+ bo->handle = handle;
+ bo->size = size;
+ bo->flags = flags;
+
+ return bo;
+}
+
+/*
+ * Destroy a rockchip buffer object.
+ *
+ * @bo: a rockchip buffer object to be destroyed.
+ */
+void rockchip_bo_destroy(struct rockchip_bo *bo)
+{
+ if (!bo)
+ return;
+
+ if (bo->vaddr)
+ munmap(bo->vaddr, bo->size);
+
+ if (bo->handle) {
+ struct drm_gem_close req = {
+ .handle = bo->handle,
+ };
+
+ drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req);
+ }
+
+ free(bo);
+}
+
+
+/*
+ * Get a rockchip buffer object from a gem global object name.
+ *
+ * @dev: a rockchip device object.
+ * @name: a gem global object name exported by another process.
+ *
+ * this interface is used to get a rockchip buffer object from a gem
+ * global object name sent by another process for buffer sharing.
+ *
+ * if true, return a rockchip buffer object else NULL.
+ *
+ */
+struct rockchip_bo *rockchip_bo_from_name(struct rockchip_device *dev,
+ uint32_t name)
+{
+ struct rockchip_bo *bo;
+ struct drm_gem_open req = {
+ .name = name,
+ };
+
+ bo = calloc(1, sizeof(*bo));
+ if (!bo) {
+ fprintf(stderr, "failed to allocate bo[%s].\n",
+ strerror(errno));
+ return NULL;
+ }
+
+ if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) {
+ fprintf(stderr, "failed to open gem object[%s].\n",
+ strerror(errno));
+ goto err_free_bo;
+ }
+
+ bo->dev = dev;
+ bo->name = name;
+ bo->handle = req.handle;
+
+ return bo;
+
+err_free_bo:
+ free(bo);
+ return NULL;
+}
+
+/*
+ * Get a gem global object name from a gem object handle.
+ *
+ * @bo: a rockchip buffer object including gem handle.
+ * @name: a gem global object name to be got by kernel driver.
+ *
+ * this interface is used to get a gem global object name from a gem object
+ * handle to a buffer that wants to share it with another process.
+ *
+ * if true, return 0 else negative.
+ */
+int rockchip_bo_get_name(struct rockchip_bo *bo, uint32_t *name)
+{
+ if (!bo->name) {
+ struct drm_gem_flink req = {
+ .handle = bo->handle,
+ };
+ int ret;
+
+ ret = drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_FLINK, &req);
+ if (ret) {
+ fprintf(stderr, "failed to get gem global name[%s].\n",
+ strerror(errno));
+ return ret;
+ }
+
+ bo->name = req.name;
+ }
+
+ *name = bo->name;
+
+ return 0;
+}
+
+uint32_t rockchip_bo_handle(struct rockchip_bo *bo)
+{
+ return bo->handle;
+}
+
+/*
+ * Mmap a buffer to user space.
+ *
+ * @bo: a rockchip buffer object including a gem object handle to be mmapped
+ * to user space.
+ *
+ * if true, user pointer mmaped else NULL.
+ */
+void *rockchip_bo_map(struct rockchip_bo *bo)
+{
+ if (!bo->vaddr) {
+ struct rockchip_device *dev = bo->dev;
+ struct drm_rockchip_gem_map_off req = {
+ .handle = bo->handle,
+ };
+ int ret;
+
+ ret = drmIoctl(dev->fd, DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET, &req);
+ if (ret) {
+ fprintf(stderr, "failed to ioctl gem map offset[%s].\n",
+ strerror(errno));
+ return NULL;
+ }
+
+ bo->vaddr = mmap(0, bo->size, PROT_READ | PROT_WRITE,
+ MAP_SHARED, dev->fd, req.offset);
+ if (bo->vaddr == MAP_FAILED) {
+ fprintf(stderr, "failed to mmap buffer[%s].\n",
+ strerror(errno));
+ return NULL;
+ }
+ }
+
+ return bo->vaddr;
+}
diff --git a/rockchip/rockchip_drm.h b/rockchip/rockchip_drm.h
new file mode 100644
index 0000000..13977d5
--- /dev/null
+++ b/rockchip/rockchip_drm.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
+ * Authors:
+ * Mark Yao <yzq@rock-chips.com>
+ *
+ * based on exynos_drm.h
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef _ROCKCHIP_DRM_H_
+#define _ROCKCHIP_DRM_H_
+
+#include <stdint.h>
+#include "drm.h"
+
+/**
+ * User-desired buffer creation information structure.
+ *
+ * @size: user-desired memory allocation size.
+ * - this size value would be page-aligned internally.
+ * @flags: user request for setting memory type or cache attributes.
+ * @handle: returned a handle to created gem object.
+ * - this handle will be set by gem module of kernel side.
+ */
+struct drm_rockchip_gem_create {
+ uint64_t size;
+ uint32_t flags;
+ uint32_t handle;
+};
+
+/**
+ * A structure for getting buffer offset.
+ *
+ * @handle: a pointer to gem object created.
+ * @pad: just padding to be 64-bit aligned.
+ * @offset: relatived offset value of the memory region allocated.
+ * - this value should be set by user.
+ */
+struct drm_rockchip_gem_map_off {
+ uint32_t handle;
+ uint32_t pad;
+ uint64_t offset;
+};
+
+#define DRM_ROCKCHIP_GEM_CREATE 0x00
+#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
+
+#define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
+
+#define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
+ DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
+
+#endif
diff --git a/rockchip/rockchip_drmif.h b/rockchip/rockchip_drmif.h
new file mode 100644
index 0000000..5c549a0
--- /dev/null
+++ b/rockchip/rockchip_drmif.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) ROCKCHIP, Inc.
+ * Author:yzq<yzq@rock-chips.com>
+ *
+ * based on exynos_drmif.h
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef ROCKCHIP_DRMIF_H_
+#define ROCKCHIP_DRMIF_H_
+
+#include <xf86drm.h>
+#include <stdint.h>
+#include "rockchip_drm.h"
+
+struct rockchip_device {
+ int fd;
+};
+
+/*
+ * Rockchip Buffer Object structure.
+ *
+ * @dev: rockchip device object allocated.
+ * @handle: a gem handle to gem object created.
+ * @flags: indicate memory allocation and cache attribute types.
+ * @size: size to the buffer created.
+ * @vaddr: user space address to a gem buffer mmaped.
+ * @name: a gem global handle from flink request.
+ */
+struct rockchip_bo {
+ struct rockchip_device *dev;
+ uint32_t handle;
+ uint32_t flags;
+ size_t size;
+ void *vaddr;
+ uint32_t name;
+};
+
+/*
+ * device related functions:
+ */
+struct rockchip_device *rockchip_device_create(int fd);
+void rockchip_device_destroy(struct rockchip_device *dev);
+
+/*
+ * buffer-object related functions:
+ */
+struct rockchip_bo *rockchip_bo_create(struct rockchip_device *dev,
+ size_t size, uint32_t flags);
+int rockchip_bo_get_info(struct rockchip_device *dev, uint32_t handle,
+ size_t *size, uint32_t *flags);
+void rockchip_bo_destroy(struct rockchip_bo *bo);
+struct rockchip_bo *rockchip_bo_from_name(struct rockchip_device *dev,
+ uint32_t name);
+int rockchip_bo_get_name(struct rockchip_bo *bo, uint32_t *name);
+uint32_t rockchip_bo_handle(struct rockchip_bo *bo);
+struct rockchip_bo *rockchip_bo_from_handle(struct rockchip_device *dev,
+ uint32_t handle, uint32_t flags, uint32_t size);
+void *rockchip_bo_map(struct rockchip_bo *bo);
+#endif /* ROCKCHIP_DRMIF_H_ */
diff --git a/tegra/Makefile.am b/tegra/Makefile.am
index 5311997..fb40be5 100644
--- a/tegra/Makefile.am
+++ b/tegra/Makefile.am
@@ -4,8 +4,7 @@
AM_CFLAGS = \
@PTHREADSTUBS_CFLAGS@ \
- $(WARN_CFLAGS) \
- -fvisibility=hidden
+ $(WARN_CFLAGS)
libdrm_tegra_ladir = $(libdir)
libdrm_tegra_la_LTLIBRARIES = libdrm_tegra.la
@@ -22,6 +21,5 @@
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_tegra.pc
-AM_TESTS_ENVIRONMENT = NM='$(NM)'
TESTS = tegra-symbol-check
EXTRA_DIST = $(TESTS)
diff --git a/tegra/meson.build b/tegra/meson.build
index 4bc454b..1f5c74b 100644
--- a/tegra/meson.build
+++ b/tegra/meson.build
@@ -24,7 +24,7 @@
include_directories : [inc_root, inc_drm],
link_with : libdrm,
dependencies : [dep_pthread_stubs, dep_atomic_ops],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
version : '0.0.0',
install : true,
)
diff --git a/tegra/private.h b/tegra/private.h
index bb6c1a5..571caa5 100644
--- a/tegra/private.h
+++ b/tegra/private.h
@@ -41,9 +41,10 @@
struct drm_tegra_bo {
struct drm_tegra *drm;
uint32_t handle;
- uint32_t offset;
+ uint64_t offset;
uint32_t flags;
uint32_t size;
+ uint32_t name;
atomic_t ref;
void *map;
};
diff --git a/tegra/tegra-symbol-check b/tegra/tegra-symbol-check
index 8539b95..509b678 100755
--- a/tegra/tegra-symbol-check
+++ b/tegra/tegra-symbol-check
@@ -1,7 +1,5 @@
#!/bin/bash
-set -u
-
# The following symbols (past the first nine) are taken from tegra.h.
FUNCS=$($NM -D --format=bsd --defined-only ${1-.libs/libdrm_tegra.so} | awk '{print $3}'| while read func; do
diff --git a/tegra/tegra.c b/tegra/tegra.c
index cf00a3c..0c86987 100644
--- a/tegra/tegra.c
+++ b/tegra/tegra.c
@@ -70,7 +70,7 @@
return 0;
}
-drm_public int drm_tegra_new(struct drm_tegra **drmp, int fd)
+int drm_tegra_new(struct drm_tegra **drmp, int fd)
{
bool supported = false;
drmVersionPtr version;
@@ -90,7 +90,7 @@
return drm_tegra_wrap(drmp, fd, false);
}
-drm_public void drm_tegra_close(struct drm_tegra *drm)
+void drm_tegra_close(struct drm_tegra *drm)
{
if (!drm)
return;
@@ -101,7 +101,7 @@
free(drm);
}
-drm_public int drm_tegra_bo_new(struct drm_tegra_bo **bop, struct drm_tegra *drm,
+int drm_tegra_bo_new(struct drm_tegra_bo **bop, struct drm_tegra *drm,
uint32_t flags, uint32_t size)
{
struct drm_tegra_gem_create args;
@@ -139,7 +139,7 @@
return 0;
}
-drm_public int drm_tegra_bo_wrap(struct drm_tegra_bo **bop, struct drm_tegra *drm,
+int drm_tegra_bo_wrap(struct drm_tegra_bo **bop, struct drm_tegra *drm,
uint32_t handle, uint32_t flags, uint32_t size)
{
struct drm_tegra_bo *bo;
@@ -162,7 +162,62 @@
return 0;
}
-drm_public struct drm_tegra_bo *drm_tegra_bo_ref(struct drm_tegra_bo *bo)
+int drm_tegra_bo_name_ref(struct drm_tegra *drm, uint32_t name, uint32_t size,
+ struct drm_tegra_bo **bop)
+{
+ struct drm_tegra_bo *bo;
+ struct drm_gem_open open_args;
+ struct drm_gem_close close_args;
+ int ret;
+
+ memset(&open_args, 0, sizeof(open_args));
+
+ open_args.name = name;
+
+ ret = drmIoctl(drm->fd, DRM_IOCTL_GEM_OPEN, &open_args);
+ if (ret)
+ return ret;
+
+ ret = drm_tegra_bo_wrap(bop, drm, open_args.handle, 0, size);
+ if (ret)
+ goto err;
+
+ (*bop)->name = name;
+
+ return 0;
+
+err:
+ memset(&close_args, 0, sizeof(close_args));
+ close_args.handle = open_args.handle;
+ drmIoctl(drm->fd, DRM_IOCTL_GEM_CLOSE, &close_args);
+
+ return ret;
+}
+
+int drm_tegra_bo_name_get(struct drm_tegra_bo *bo, uint32_t *name)
+{
+ struct drm_gem_flink args;
+ int ret;
+
+ args.handle = bo->handle;
+
+ *name = bo->name;
+ if (*name && *name != ~0U)
+ return 0;
+
+ ret = drmIoctl(bo->drm->fd, DRM_IOCTL_GEM_FLINK, &args);
+ if (ret) {
+ *name = 0;
+ return ret;
+ }
+
+ bo->name = args.name;
+ *name = bo->name;
+
+ return 0;
+}
+
+struct drm_tegra_bo *drm_tegra_bo_ref(struct drm_tegra_bo *bo)
{
if (bo)
atomic_inc(&bo->ref);
@@ -170,13 +225,13 @@
return bo;
}
-drm_public void drm_tegra_bo_unref(struct drm_tegra_bo *bo)
+void drm_tegra_bo_unref(struct drm_tegra_bo *bo)
{
if (bo && atomic_dec_and_test(&bo->ref))
drm_tegra_bo_free(bo);
}
-drm_public int drm_tegra_bo_get_handle(struct drm_tegra_bo *bo, uint32_t *handle)
+int drm_tegra_bo_get_handle(struct drm_tegra_bo *bo, uint32_t *handle)
{
if (!bo || !handle)
return -EINVAL;
@@ -186,7 +241,7 @@
return 0;
}
-drm_public int drm_tegra_bo_map(struct drm_tegra_bo *bo, void **ptr)
+int drm_tegra_bo_map(struct drm_tegra_bo *bo, void **ptr)
{
struct drm_tegra *drm = bo->drm;
@@ -218,7 +273,7 @@
return 0;
}
-drm_public int drm_tegra_bo_unmap(struct drm_tegra_bo *bo)
+int drm_tegra_bo_unmap(struct drm_tegra_bo *bo)
{
if (!bo)
return -EINVAL;
@@ -234,7 +289,7 @@
return 0;
}
-drm_public int drm_tegra_bo_get_flags(struct drm_tegra_bo *bo, uint32_t *flags)
+int drm_tegra_bo_get_flags(struct drm_tegra_bo *bo, uint32_t *flags)
{
struct drm_tegra_gem_get_flags args;
struct drm_tegra *drm = bo->drm;
@@ -257,7 +312,7 @@
return 0;
}
-drm_public int drm_tegra_bo_set_flags(struct drm_tegra_bo *bo, uint32_t flags)
+int drm_tegra_bo_set_flags(struct drm_tegra_bo *bo, uint32_t flags)
{
struct drm_tegra_gem_get_flags args;
struct drm_tegra *drm = bo->drm;
@@ -278,7 +333,7 @@
return 0;
}
-drm_public int drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo,
+int drm_tegra_bo_get_tiling(struct drm_tegra_bo *bo,
struct drm_tegra_bo_tiling *tiling)
{
struct drm_tegra_gem_get_tiling args;
@@ -304,7 +359,7 @@
return 0;
}
-drm_public int drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo,
+int drm_tegra_bo_set_tiling(struct drm_tegra_bo *bo,
const struct drm_tegra_bo_tiling *tiling)
{
struct drm_tegra_gem_set_tiling args;
diff --git a/tegra/tegra.h b/tegra/tegra.h
index 31b0995..e10eab7 100644
--- a/tegra/tegra.h
+++ b/tegra/tegra.h
@@ -38,6 +38,11 @@
uint32_t flags, uint32_t size);
int drm_tegra_bo_wrap(struct drm_tegra_bo **bop, struct drm_tegra *drm,
uint32_t handle, uint32_t flags, uint32_t size);
+
+int drm_tegra_bo_name_ref(struct drm_tegra *drm, uint32_t name, uint32_t size,
+ struct drm_tegra_bo **bop);
+int drm_tegra_bo_name_get(struct drm_tegra_bo *bo, uint32_t *name);
+
struct drm_tegra_bo *drm_tegra_bo_ref(struct drm_tegra_bo *bo);
void drm_tegra_bo_unref(struct drm_tegra_bo *bo);
int drm_tegra_bo_get_handle(struct drm_tegra_bo *bo, uint32_t *handle);
diff --git a/tests/Makefile.am b/tests/Makefile.am
index d274a3e..f2bb4d4 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -1,7 +1,7 @@
SUBDIRS = util kms modeprint proptest modetest vbltest
if HAVE_LIBKMS
-SUBDIRS += kmstest
+SUBDIRS += kmstest planetest
endif
if HAVE_RADEON
@@ -32,7 +32,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)
@@ -44,10 +43,5 @@
random
check_PROGRAMS = \
- $(TESTS)
-
-if HAVE_INSTALL_TESTS
-bin_PROGRAMS = drmdevice
-else
-check_PROGRAMS += drmdevice
-endif
+ $(TESTS) \
+ drmdevice
diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 920882d..e79c1bd 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -1,5 +1,4 @@
AM_CFLAGS = \
- -fvisibility=hidden \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)/amdgpu \
-I $(top_srcdir) \
@@ -33,6 +32,4 @@
vcn_tests.c \
uve_ib.h \
deadlock_tests.c \
- vm_tests.c \
- ras_tests.c \
- syncobj_tests.c
+ vm_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 73403fb..96fcd68 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,8 +56,6 @@
#define UVD_ENC_TESTS_STR "UVD ENC Tests"
#define DEADLOCK_TESTS_STR "Deadlock Tests"
#define VM_TESTS_STR "VM Tests"
-#define RAS_TESTS_STR "RAS Tests"
-#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
/**
* Open handles for amdgpu devices
@@ -118,18 +116,6 @@
.pCleanupFunc = suite_vm_tests_clean,
.pTests = vm_tests,
},
- {
- .pName = RAS_TESTS_STR,
- .pInitFunc = suite_ras_tests_init,
- .pCleanupFunc = suite_ras_tests_clean,
- .pTests = ras_tests,
- },
- {
- .pName = SYNCOBJ_TIMELINE_TESTS_STR,
- .pInitFunc = suite_syncobj_timeline_tests_init,
- .pCleanupFunc = suite_syncobj_timeline_tests_clean,
- .pTests = syncobj_timeline_tests,
- },
CU_SUITE_INFO_NULL,
};
@@ -179,14 +165,6 @@
.pName = VM_TESTS_STR,
.pActive = suite_vm_tests_enable,
},
- {
- .pName = RAS_TESTS_STR,
- .pActive = suite_ras_tests_enable,
- },
- {
- .pName = SYNCOBJ_TIMELINE_TESTS_STR,
- .pActive = suite_syncobj_timeline_tests_enable,
- },
};
@@ -256,7 +234,7 @@
static const char options[] = "hlrps:t:b:d:f";
/* Open AMD devices.
- * Return the number of AMD device opened.
+ * Return the number of AMD device openned.
*/
static int amdgpu_open_devices(int open_render_node)
{
@@ -344,7 +322,7 @@
int i;
drmDevicePtr device;
- /* Open the first AMD device to print driver information. */
+ /* Open the first AMD devcie to print driver information. */
if (drm_amdgpu[0] >=0) {
/* Display AMD driver version information.*/
drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]);
@@ -444,12 +422,7 @@
* BUG: Compute ring stalls and never recovers when the address is
* written after the command already submitted
*/
- if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
- "compute ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE))
- fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
- if (amdgpu_set_test_active(DEADLOCK_TESTS_STR,
- "sdma ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE))
+ if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, "compute ring block test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
if (amdgpu_set_test_active(BO_TESTS_STR, "Metadata", CU_FALSE))
@@ -462,16 +435,6 @@
if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE))
fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
- /* This test was ran on GFX9 only */
- if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
- if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test", CU_FALSE))
- fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
-
- /* This test was ran on GFX9 only */
- if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV)
- if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE))
- fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg());
}
/* The main() function for setting up and running the tests.
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index 36675ea..6287573 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -30,7 +30,7 @@
/**
* Define max. number of card in system which we are able to handle
*/
-#define MAX_CARDS_SUPPORTED 128
+#define MAX_CARDS_SUPPORTED 4
/* Forward reference for array to keep "drm" handles */
extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
@@ -194,49 +194,6 @@
*/
extern CU_TestInfo vm_tests[];
-
-/**
- * Initialize ras test suite
- */
-int suite_ras_tests_init();
-
-/**
- * Deinitialize deadlock test suite
- */
-int suite_ras_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_ras_tests_enable(void);
-
-/**
- * Tests in ras test suite
- */
-extern CU_TestInfo ras_tests[];
-
-
-/**
- * Initialize syncobj timeline test suite
- */
-int suite_syncobj_timeline_tests_init();
-
-/**
- * Deinitialize syncobj timeline test suite
- */
-int suite_syncobj_timeline_tests_clean();
-
-/**
- * Decide if the suite is enabled by default or not.
- */
-CU_BOOL suite_syncobj_timeline_tests_enable(void);
-
-/**
- * Tests in syncobj timeline test suite
- */
-extern CU_TestInfo syncobj_timeline_tests[];
-
-
/**
* Helper functions
*/
@@ -250,9 +207,11 @@
amdgpu_va_handle *va_handle)
{
struct amdgpu_bo_alloc_request req = {0};
- amdgpu_bo_handle buf_handle = NULL;
+ amdgpu_bo_handle buf_handle;
int r;
+ CU_ASSERT_NOT_EQUAL(vmc_addr, NULL);
+
req.alloc_size = size;
req.phys_alignment = alignment;
req.preferred_heap = type;
@@ -260,36 +219,17 @@
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
CU_ASSERT_EQUAL(r, 0);
- if (r)
- return NULL;
- if (vmc_addr && va_handle) {
- r = amdgpu_va_range_alloc(device_handle,
- amdgpu_gpu_va_range_general,
- size, alignment, 0, vmc_addr,
- va_handle, 0);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- goto error_free_bo;
+ r = amdgpu_va_range_alloc(device_handle,
+ amdgpu_gpu_va_range_general,
+ size, alignment, 0, vmc_addr,
+ va_handle, 0);
+ CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0,
- AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- goto error_free_va;
- }
+ r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
+ CU_ASSERT_EQUAL(r, 0);
return buf_handle;
-
-error_free_va:
- r = amdgpu_va_range_free(*va_handle);
- CU_ASSERT_EQUAL(r, 0);
-
-error_free_bo:
- r = amdgpu_bo_free(buf_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- return NULL;
}
static inline int gpu_mem_free(amdgpu_bo_handle bo,
@@ -299,26 +239,16 @@
{
int r;
- if (!bo)
- return 0;
+ r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+ CU_ASSERT_EQUAL(r, 0);
- if (va_handle) {
- r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0,
- AMDGPU_VA_OP_UNMAP);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- return r;
-
- r = amdgpu_va_range_free(va_handle);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- return r;
- }
+ r = amdgpu_va_range_free(va_handle);
+ CU_ASSERT_EQUAL(r, 0);
r = amdgpu_bo_free(bo);
CU_ASSERT_EQUAL(r, 0);
- return r;
+ return 0;
}
static inline int
@@ -344,20 +274,57 @@
return 0;
}
-int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
- unsigned alignment, unsigned heap, uint64_t alloc_flags,
- uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
- uint64_t *mc_address,
- amdgpu_va_handle *va_handle);
-
static inline int
amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
- unsigned alignment, unsigned heap, uint64_t alloc_flags,
+ unsigned alignment, unsigned heap, uint64_t flags,
amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
amdgpu_va_handle *va_handle)
{
- return amdgpu_bo_alloc_and_map_raw(dev, size, alignment, heap,
- alloc_flags, 0, bo, cpu, mc_address, va_handle);
+ struct amdgpu_bo_alloc_request request = {};
+ amdgpu_bo_handle buf_handle;
+ amdgpu_va_handle handle;
+ uint64_t vmc_addr;
+ int r;
+
+ request.alloc_size = size;
+ request.phys_alignment = alignment;
+ request.preferred_heap = heap;
+ request.flags = flags;
+
+ r = amdgpu_bo_alloc(dev, &request, &buf_handle);
+ if (r)
+ return r;
+
+ r = amdgpu_va_range_alloc(dev,
+ amdgpu_gpu_va_range_general,
+ size, alignment, 0, &vmc_addr,
+ &handle, 0);
+ if (r)
+ goto error_va_alloc;
+
+ r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP);
+ if (r)
+ goto error_va_map;
+
+ r = amdgpu_bo_cpu_map(buf_handle, cpu);
+ if (r)
+ goto error_cpu_map;
+
+ *bo = buf_handle;
+ *mc_address = vmc_addr;
+ *va_handle = handle;
+
+ return 0;
+
+error_cpu_map:
+ amdgpu_bo_cpu_unmap(buf_handle);
+
+error_va_map:
+ amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+
+error_va_alloc:
+ amdgpu_bo_free(buf_handle);
+ return r;
}
static inline int
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index 2d47269..1adbddd 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -33,7 +33,6 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
-#include "util_math.h"
static amdgpu_device_handle device_handle;
static uint32_t major_version;
@@ -49,8 +48,6 @@
static void amdgpu_semaphore_test(void);
static void amdgpu_sync_dependency_test(void);
static void amdgpu_bo_eviction_test(void);
-static void amdgpu_dispatch_test(void);
-static void amdgpu_draw_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -72,8 +69,6 @@
{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
{ "SW semaphore Test", amdgpu_semaphore_test },
{ "Sync dependency Test", amdgpu_sync_dependency_test },
- { "Dispatch Test", amdgpu_dispatch_test },
- { "Draw Test", amdgpu_draw_test },
CU_TEST_INFO_NULL,
};
#define BUFFER_SIZE (8 * 1024)
@@ -121,7 +116,6 @@
#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
(((op) & 0xFF) << 8) | \
((n) & 0x3FFF) << 16)
-#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
/* Packet 3 types */
#define PACKET3_NOP 0x10
@@ -250,11 +244,8 @@
#define PACKET3_SET_SH_REG_START 0x00002c00
#define PACKET3_DISPATCH_DIRECT 0x15
-#define PACKET3_EVENT_WRITE 0x46
-#define PACKET3_ACQUIRE_MEM 0x58
-#define PACKET3_SET_CONTEXT_REG 0x69
-#define PACKET3_SET_UCONFIG_REG 0x79
-#define PACKET3_DRAW_INDEX_AUTO 0x2D
+
+
/* gfx 8 */
#define mmCOMPUTE_PGM_LO 0x2e0c
#define mmCOMPUTE_PGM_RSRC1 0x2e12
@@ -294,228 +285,6 @@
#define CODE_OFFSET 512
#define DATA_OFFSET 1024
-enum cs_type {
- CS_BUFFERCLEAR,
- CS_BUFFERCOPY
-};
-
-static const uint32_t bufferclear_cs_shader_gfx9[] = {
- 0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205,
- 0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100,
- 0xBF810000
-};
-
-static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
- {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 },
- {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 },
- {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
- {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
- {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
-};
-
-static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
-
-static const uint32_t buffercopy_cs_shader_gfx9[] = {
- 0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100,
- 0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
-};
-
-static const uint32_t preamblecache_gfx9[] = {
- 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0,
- 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000,
- 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0,
- 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0,
- 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0,
- 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0,
- 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0,
- 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
- 0xc0026900, 0x311, 0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
- 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0,
- 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0,
- 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0,
- 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
- 0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
- 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0,
- 0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0,
- 0xc0017900, 0x24b, 0x0
-};
-
-enum ps_type {
- PS_CONST,
- PS_TEX
-};
-
-static const uint32_t ps_const_shader_gfx9[] = {
- 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203,
- 0xD2960000, 0x00020300, 0xD2960001, 0x00020702,
- 0xC4001C0F, 0x00000100, 0xBF810000
-};
-
-static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6;
-
-static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = {
- {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 },
- { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 },
- { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 },
- { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 },
- { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 },
- { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 }
- }
-};
-
-static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = {
- 0x00000004
-};
-
-static const uint32_t ps_num_sh_registers_gfx9 = 2;
-
-static const uint32_t ps_const_sh_registers_gfx9[][2] = {
- {0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 },
- {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 }
-};
-
-static const uint32_t ps_num_context_registers_gfx9 = 7;
-
-static const uint32_t ps_const_context_reg_gfx9[][2] = {
- {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
- {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 },
- {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
- {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
- {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
- {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
- {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
-};
-
-static const uint32_t ps_tex_shader_gfx9[] = {
- 0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000,
- 0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00,
- 0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000,
- 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F,
- 0x00000100, 0xBF810000
-};
-
-static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = {
- 0x0000000B
-};
-
-static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6;
-
-static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = {
- {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 },
- { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 },
- { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 },
- { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 },
- { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 },
- { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 },
- { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 }
- }
-};
-
-static const uint32_t ps_tex_sh_registers_gfx9[][2] = {
- {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 },
- {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 }
-};
-
-static const uint32_t ps_tex_context_reg_gfx9[][2] = {
- {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 },
- {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 },
- {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F },
- {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 },
- {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 },
- {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */},
- {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 }
-};
-
-static const uint32_t vs_RectPosTexFast_shader_gfx9[] = {
- 0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100,
- 0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206,
- 0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080,
- 0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003,
- 0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101,
- 0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903,
- 0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100,
- 0xC400020F, 0x05060403, 0xBF810000
-};
-
-static const uint32_t cached_cmd_gfx9[] = {
- 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
- 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
- 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
- 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12,
- 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
- 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
- 0xc0026900, 0x292, 0x20, 0x60201b8,
- 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0
-};
-
-int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
- unsigned alignment, unsigned heap, uint64_t alloc_flags,
- uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
- uint64_t *mc_address,
- amdgpu_va_handle *va_handle)
-{
- struct amdgpu_bo_alloc_request request = {};
- amdgpu_bo_handle buf_handle;
- amdgpu_va_handle handle;
- uint64_t vmc_addr;
- int r;
-
- request.alloc_size = size;
- request.phys_alignment = alignment;
- request.preferred_heap = heap;
- request.flags = alloc_flags;
-
- r = amdgpu_bo_alloc(dev, &request, &buf_handle);
- if (r)
- return r;
-
- r = amdgpu_va_range_alloc(dev,
- amdgpu_gpu_va_range_general,
- size, alignment, 0, &vmc_addr,
- &handle, 0);
- if (r)
- goto error_va_alloc;
-
- r = amdgpu_bo_va_op_raw(dev, buf_handle, 0, ALIGN(size, getpagesize()), vmc_addr,
- AMDGPU_VM_PAGE_READABLE |
- AMDGPU_VM_PAGE_WRITEABLE |
- AMDGPU_VM_PAGE_EXECUTABLE |
- mapping_flags,
- AMDGPU_VA_OP_MAP);
- if (r)
- goto error_va_map;
-
- r = amdgpu_bo_cpu_map(buf_handle, cpu);
- if (r)
- goto error_cpu_map;
-
- *bo = buf_handle;
- *mc_address = vmc_addr;
- *va_handle = handle;
-
- return 0;
-
- error_cpu_map:
- amdgpu_bo_cpu_unmap(buf_handle);
-
- error_va_map:
- amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
-
- error_va_alloc:
- amdgpu_bo_free(buf_handle);
- return r;
-}
-
-
int suite_basic_tests_init(void)
{
@@ -2053,1061 +1822,3 @@
free(ibs_request.dependencies);
}
-
-static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
- int cs_type)
-{
- uint32_t shader_size;
- const uint32_t *shader;
-
- switch (cs_type) {
- case CS_BUFFERCLEAR:
- shader = bufferclear_cs_shader_gfx9;
- shader_size = sizeof(bufferclear_cs_shader_gfx9);
- break;
- case CS_BUFFERCOPY:
- shader = buffercopy_cs_shader_gfx9;
- shader_size = sizeof(buffercopy_cs_shader_gfx9);
- break;
- default:
- return -1;
- break;
- }
-
- memcpy(ptr, shader, shader_size);
- return 0;
-}
-
-static int amdgpu_dispatch_init(uint32_t *ptr, uint32_t ip_type)
-{
- int i = 0;
-
- /* Write context control and load shadowing register if necessary */
- if (ip_type == AMDGPU_HW_IP_GFX) {
- ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
- ptr[i++] = 0x80000000;
- ptr[i++] = 0x80000000;
- }
-
- /* Issue commands to set default compute state. */
- /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
- ptr[i++] = 0x204;
- i += 3;
- /* clear mmCOMPUTE_RESOURCE_LIMITS */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
- ptr[i++] = 0x215;
- ptr[i++] = 0;
- /* clear mmCOMPUTE_TMPRING_SIZE */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
- ptr[i++] = 0x218;
- ptr[i++] = 0;
-
- return i;
-}
-
-static int amdgpu_dispatch_write_cumask(uint32_t *ptr)
-{
- int i = 0;
-
- /* Issue commands to set cu mask used in current dispatch */
- /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
- ptr[i++] = 0x216;
- ptr[i++] = 0xffffffff;
- ptr[i++] = 0xffffffff;
- /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
- ptr[i++] = 0x219;
- ptr[i++] = 0xffffffff;
- ptr[i++] = 0xffffffff;
-
- return i;
-}
-
-static int amdgpu_dispatch_write2hw(uint32_t *ptr, uint64_t shader_addr)
-{
- int i, j;
-
- i = 0;
-
- /* Writes shader state to HW */
- /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
- ptr[i++] = 0x20c;
- ptr[i++] = (shader_addr >> 8);
- ptr[i++] = (shader_addr >> 40);
- /* write sh regs*/
- for (j = 0; j < bufferclear_cs_shader_registers_num_gfx9; j++) {
- ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
- /* - Gfx9ShRegBase */
- ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][0] - 0x2c00;
- ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1];
- }
-
- return i;
-}
-
-static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
- uint32_t ip_type,
- uint32_t ring)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle bo_dst, bo_shader, bo_cmd, resources[3];
- volatile unsigned char *ptr_dst;
- void *ptr_shader;
- uint32_t *ptr_cmd;
- uint64_t mc_address_dst, mc_address_shader, mc_address_cmd;
- amdgpu_va_handle va_dst, va_shader, va_cmd;
- int i, r;
- int bo_dst_size = 16384;
- int bo_shader_size = 4096;
- int bo_cmd_size = 4096;
- struct amdgpu_cs_request ibs_request = {0};
- struct amdgpu_cs_ib_info ib_info= {0};
- amdgpu_bo_list_handle bo_list;
- struct amdgpu_cs_fence fence_status = {0};
- uint32_t expired;
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &bo_cmd, (void **)&ptr_cmd,
- &mc_address_cmd, &va_cmd);
- CU_ASSERT_EQUAL(r, 0);
- memset(ptr_cmd, 0, bo_cmd_size);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader, &ptr_shader,
- &mc_address_shader, &va_shader);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_dst, (void **)&ptr_dst,
- &mc_address_dst, &va_dst);
- CU_ASSERT_EQUAL(r, 0);
-
- i = 0;
- i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
-
- /* Issue commands to set cu mask used in current dispatch */
- i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
-
- /* Writes shader state to HW */
- i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
-
- /* Write constant data */
- /* Writes the UAV constant data to the SGPRs. */
- ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0x240;
- ptr_cmd[i++] = mc_address_dst;
- ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
- ptr_cmd[i++] = 0x400;
- ptr_cmd[i++] = 0x74fac;
-
- /* Sets a range of pixel shader constants */
- ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0x244;
- ptr_cmd[i++] = 0x22222222;
- ptr_cmd[i++] = 0x22222222;
- ptr_cmd[i++] = 0x22222222;
- ptr_cmd[i++] = 0x22222222;
-
- /* dispatch direct command */
- ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
- ptr_cmd[i++] = 0x10;
- ptr_cmd[i++] = 1;
- ptr_cmd[i++] = 1;
- ptr_cmd[i++] = 1;
-
- while (i & 7)
- ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
-
- resources[0] = bo_dst;
- resources[1] = bo_shader;
- resources[2] = bo_cmd;
- r = amdgpu_bo_list_create(device_handle, 3, resources, NULL, &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ib_info.ib_mc_address = mc_address_cmd;
- ib_info.size = i;
- ibs_request.ip_type = ip_type;
- ibs_request.ring = ring;
- ibs_request.resources = bo_list;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.fence_info.handle = NULL;
-
- /* submit CS */
- r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- fence_status.ip_type = ip_type;
- fence_status.ip_instance = 0;
- fence_status.ring = ring;
- fence_status.context = context_handle;
- fence_status.fence = ibs_request.seq_no;
-
- /* wait for IB accomplished */
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,
- 0, &expired);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(expired, true);
-
- /* verify if memset test result meets with expected */
- i = 0;
- while(i < bo_dst_size) {
- CU_ASSERT_EQUAL(ptr_dst[i++], 0x22);
- }
-
- r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
- uint32_t ip_type,
- uint32_t ring)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
- volatile unsigned char *ptr_dst;
- void *ptr_shader;
- unsigned char *ptr_src;
- uint32_t *ptr_cmd;
- uint64_t mc_address_src, mc_address_dst, mc_address_shader, mc_address_cmd;
- amdgpu_va_handle va_src, va_dst, va_shader, va_cmd;
- int i, r;
- int bo_dst_size = 16384;
- int bo_shader_size = 4096;
- int bo_cmd_size = 4096;
- struct amdgpu_cs_request ibs_request = {0};
- struct amdgpu_cs_ib_info ib_info= {0};
- uint32_t expired;
- amdgpu_bo_list_handle bo_list;
- struct amdgpu_cs_fence fence_status = {0};
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &bo_cmd, (void **)&ptr_cmd,
- &mc_address_cmd, &va_cmd);
- CU_ASSERT_EQUAL(r, 0);
- memset(ptr_cmd, 0, bo_cmd_size);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader, &ptr_shader,
- &mc_address_shader, &va_shader);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_src, (void **)&ptr_src,
- &mc_address_src, &va_src);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_dst, (void **)&ptr_dst,
- &mc_address_dst, &va_dst);
- CU_ASSERT_EQUAL(r, 0);
-
- memset(ptr_src, 0x55, bo_dst_size);
-
- i = 0;
- i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
-
- /* Issue commands to set cu mask used in current dispatch */
- i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
-
- /* Writes shader state to HW */
- i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
-
- /* Write constant data */
- /* Writes the texture resource constants data to the SGPRs */
- ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0x240;
- ptr_cmd[i++] = mc_address_src;
- ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
- ptr_cmd[i++] = 0x400;
- ptr_cmd[i++] = 0x74fac;
-
- /* Writes the UAV constant data to the SGPRs. */
- ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0x244;
- ptr_cmd[i++] = mc_address_dst;
- ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
- ptr_cmd[i++] = 0x400;
- ptr_cmd[i++] = 0x74fac;
-
- /* dispatch direct command */
- ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
- ptr_cmd[i++] = 0x10;
- ptr_cmd[i++] = 1;
- ptr_cmd[i++] = 1;
- ptr_cmd[i++] = 1;
-
- while (i & 7)
- ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
-
- resources[0] = bo_shader;
- resources[1] = bo_src;
- resources[2] = bo_dst;
- resources[3] = bo_cmd;
- r = amdgpu_bo_list_create(device_handle, 4, resources, NULL, &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ib_info.ib_mc_address = mc_address_cmd;
- ib_info.size = i;
- ibs_request.ip_type = ip_type;
- ibs_request.ring = ring;
- ibs_request.resources = bo_list;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.fence_info.handle = NULL;
- r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
- CU_ASSERT_EQUAL(r, 0);
-
- fence_status.ip_type = ip_type;
- fence_status.ip_instance = 0;
- fence_status.ring = ring;
- fence_status.context = context_handle;
- fence_status.fence = ibs_request.seq_no;
-
- /* wait for IB accomplished */
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,
- 0, &expired);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(expired, true);
-
- /* verify if memcpy test result meets with expected */
- i = 0;
- while(i < bo_dst_size) {
- CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]);
- i++;
- }
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_dst_size);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-static void amdgpu_dispatch_test(void)
-{
- int r;
- struct drm_amdgpu_info_hw_ip info;
- uint32_t ring_id;
-
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
- CU_ASSERT_EQUAL(r, 0);
-
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
- amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
- }
-
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
- CU_ASSERT_EQUAL(r, 0);
-
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
- amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
- }
-}
-
-static int amdgpu_draw_load_ps_shader(uint8_t *ptr, int ps_type)
-{
- int i;
- uint32_t shader_offset= 256;
- uint32_t mem_offset, patch_code_offset;
- uint32_t shader_size, patchinfo_code_size;
- const uint32_t *shader;
- const uint32_t *patchinfo_code;
- const uint32_t *patchcode_offset;
-
- switch (ps_type) {
- case PS_CONST:
- shader = ps_const_shader_gfx9;
- shader_size = sizeof(ps_const_shader_gfx9);
- patchinfo_code = (const uint32_t *)ps_const_shader_patchinfo_code_gfx9;
- patchinfo_code_size = ps_const_shader_patchinfo_code_size_gfx9;
- patchcode_offset = ps_const_shader_patchinfo_offset_gfx9;
- break;
- case PS_TEX:
- shader = ps_tex_shader_gfx9;
- shader_size = sizeof(ps_tex_shader_gfx9);
- patchinfo_code = (const uint32_t *)ps_tex_shader_patchinfo_code_gfx9;
- patchinfo_code_size = ps_tex_shader_patchinfo_code_size_gfx9;
- patchcode_offset = ps_tex_shader_patchinfo_offset_gfx9;
- break;
- default:
- return -1;
- break;
- }
-
- /* write main shader program */
- for (i = 0 ; i < 10; i++) {
- mem_offset = i * shader_offset;
- memcpy(ptr + mem_offset, shader, shader_size);
- }
-
- /* overwrite patch codes */
- for (i = 0 ; i < 10; i++) {
- mem_offset = i * shader_offset + patchcode_offset[0] * sizeof(uint32_t);
- patch_code_offset = i * patchinfo_code_size;
- memcpy(ptr + mem_offset,
- patchinfo_code + patch_code_offset,
- patchinfo_code_size * sizeof(uint32_t));
- }
-
- return 0;
-}
-
-/* load RectPosTexFast_VS */
-static int amdgpu_draw_load_vs_shader(uint8_t *ptr)
-{
- const uint32_t *shader;
- uint32_t shader_size;
-
- shader = vs_RectPosTexFast_shader_gfx9;
- shader_size = sizeof(vs_RectPosTexFast_shader_gfx9);
-
- memcpy(ptr, shader, shader_size);
-
- return 0;
-}
-
-static int amdgpu_draw_init(uint32_t *ptr)
-{
- int i = 0;
- const uint32_t *preamblecache_ptr;
- uint32_t preamblecache_size;
-
- /* Write context control and load shadowing register if necessary */
- ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
- ptr[i++] = 0x80000000;
- ptr[i++] = 0x80000000;
-
- preamblecache_ptr = preamblecache_gfx9;
- preamblecache_size = sizeof(preamblecache_gfx9);
-
- memcpy(ptr + i, preamblecache_ptr, preamblecache_size);
- return i + preamblecache_size/sizeof(uint32_t);
-}
-
-static int amdgpu_draw_setup_and_write_drawblt_surf_info(uint32_t *ptr,
- uint64_t dst_addr)
-{
- int i = 0;
-
- /* setup color buffer */
- /* offset reg
- 0xA318 CB_COLOR0_BASE
- 0xA319 CB_COLOR0_BASE_EXT
- 0xA31A CB_COLOR0_ATTRIB2
- 0xA31B CB_COLOR0_VIEW
- 0xA31C CB_COLOR0_INFO
- 0xA31D CB_COLOR0_ATTRIB
- 0xA31E CB_COLOR0_DCC_CONTROL
- 0xA31F CB_COLOR0_CMASK
- 0xA320 CB_COLOR0_CMASK_BASE_EXT
- 0xA321 CB_COLOR0_FMASK
- 0xA322 CB_COLOR0_FMASK_BASE_EXT
- 0xA323 CB_COLOR0_CLEAR_WORD0
- 0xA324 CB_COLOR0_CLEAR_WORD1
- 0xA325 CB_COLOR0_DCC_BASE
- 0xA326 CB_COLOR0_DCC_BASE_EXT */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15);
- ptr[i++] = 0x318;
- ptr[i++] = dst_addr >> 8;
- ptr[i++] = dst_addr >> 40;
- ptr[i++] = 0x7c01f;
- ptr[i++] = 0;
- ptr[i++] = 0x50438;
- ptr[i++] = 0x10140000;
- i += 9;
-
- /* mmCB_MRT0_EPITCH */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x1e8;
- ptr[i++] = 0x1f;
-
- /* 0xA32B CB_COLOR1_BASE */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x32b;
- ptr[i++] = 0;
-
- /* 0xA33A CB_COLOR1_BASE */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x33a;
- ptr[i++] = 0;
-
- /* SPI_SHADER_COL_FORMAT */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x1c5;
- ptr[i++] = 9;
-
- /* Setup depth buffer */
- /* mmDB_Z_INFO */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
- ptr[i++] = 0xe;
- i += 2;
-
- return i;
-}
-
-static int amdgpu_draw_setup_and_write_drawblt_state(uint32_t *ptr)
-{
- int i = 0;
- const uint32_t *cached_cmd_ptr;
- uint32_t cached_cmd_size;
-
- /* mmPA_SC_TILE_STEERING_OVERRIDE */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0xd7;
- ptr[i++] = 0;
-
- ptr[i++] = 0xffff1000;
- ptr[i++] = 0xc0021000;
-
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0xd7;
- ptr[i++] = 1;
-
- /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16);
- ptr[i++] = 0x2fe;
- i += 16;
-
- /* mmPA_SC_CENTROID_PRIORITY_0 */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
- ptr[i++] = 0x2f5;
- i += 2;
-
- cached_cmd_ptr = cached_cmd_gfx9;
- cached_cmd_size = sizeof(cached_cmd_gfx9);
-
- memcpy(ptr + i, cached_cmd_ptr, cached_cmd_size);
- i += cached_cmd_size/sizeof(uint32_t);
-
- return i;
-}
-
-static int amdgpu_draw_vs_RectPosTexFast_write2hw(uint32_t *ptr,
- int ps_type,
- uint64_t shader_addr)
-{
- int i = 0;
-
- /* mmPA_CL_VS_OUT_CNTL */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x207;
- ptr[i++] = 0;
-
- /* mmSPI_SHADER_PGM_RSRC3_VS */
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
- ptr[i++] = 0x46;
- ptr[i++] = 0xffff;
-
- /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2);
- ptr[i++] = 0x48;
- ptr[i++] = shader_addr >> 8;
- ptr[i++] = shader_addr >> 40;
-
- /* mmSPI_SHADER_PGM_RSRC1_VS */
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
- ptr[i++] = 0x4a;
- ptr[i++] = 0xc0081;
- /* mmSPI_SHADER_PGM_RSRC2_VS */
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
- ptr[i++] = 0x4b;
- ptr[i++] = 0x18;
-
- /* mmSPI_VS_OUT_CONFIG */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x1b1;
- ptr[i++] = 2;
-
- /* mmSPI_SHADER_POS_FORMAT */
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x1c3;
- ptr[i++] = 4;
-
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
- ptr[i++] = 0x4c;
- i += 2;
- ptr[i++] = 0x42000000;
- ptr[i++] = 0x42000000;
-
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
- ptr[i++] = 0x50;
- i += 2;
- if (ps_type == PS_CONST) {
- i += 2;
- } else if (ps_type == PS_TEX) {
- ptr[i++] = 0x3f800000;
- ptr[i++] = 0x3f800000;
- }
-
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 4);
- ptr[i++] = 0x54;
- i += 4;
-
- return i;
-}
-
-static int amdgpu_draw_ps_write2hw(uint32_t *ptr,
- int ps_type,
- uint64_t shader_addr)
-{
- int i, j;
- const uint32_t *sh_registers;
- const uint32_t *context_registers;
- uint32_t num_sh_reg, num_context_reg;
-
- if (ps_type == PS_CONST) {
- sh_registers = (const uint32_t *)ps_const_sh_registers_gfx9;
- context_registers = (const uint32_t *)ps_const_context_reg_gfx9;
- num_sh_reg = ps_num_sh_registers_gfx9;
- num_context_reg = ps_num_context_registers_gfx9;
- } else if (ps_type == PS_TEX) {
- sh_registers = (const uint32_t *)ps_tex_sh_registers_gfx9;
- context_registers = (const uint32_t *)ps_tex_context_reg_gfx9;
- num_sh_reg = ps_num_sh_registers_gfx9;
- num_context_reg = ps_num_context_registers_gfx9;
- }
-
- i = 0;
-
- /* 0x2c07 SPI_SHADER_PGM_RSRC3_PS
- 0x2c08 SPI_SHADER_PGM_LO_PS
- 0x2c09 SPI_SHADER_PGM_HI_PS */
- shader_addr += 256 * 9;
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3);
- ptr[i++] = 0x7;
- ptr[i++] = 0xffff;
- ptr[i++] = shader_addr >> 8;
- ptr[i++] = shader_addr >> 40;
-
- for (j = 0; j < num_sh_reg; j++) {
- ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1);
- ptr[i++] = sh_registers[j * 2] - 0x2c00;
- ptr[i++] = sh_registers[j * 2 + 1];
- }
-
- for (j = 0; j < num_context_reg; j++) {
- if (context_registers[j * 2] != 0xA1C5) {
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = context_registers[j * 2] - 0xa000;
- ptr[i++] = context_registers[j * 2 + 1];
- }
-
- if (context_registers[j * 2] == 0xA1B4) {
- ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
- ptr[i++] = 0x1b3;
- ptr[i++] = 2;
- }
- }
-
- return i;
-}
-
-static int amdgpu_draw_draw(uint32_t *ptr)
-{
- int i = 0;
-
- /* mmIA_MULTI_VGT_PARAM */
- ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
- ptr[i++] = 0x40000258;
- ptr[i++] = 0xd00ff;
-
- /* mmVGT_PRIMITIVE_TYPE */
- ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
- ptr[i++] = 0x10000242;
- ptr[i++] = 0x11;
-
- ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1);
- ptr[i++] = 3;
- ptr[i++] = 2;
-
- return i;
-}
-
-void amdgpu_memset_draw(amdgpu_device_handle device_handle,
- amdgpu_bo_handle bo_shader_ps,
- amdgpu_bo_handle bo_shader_vs,
- uint64_t mc_address_shader_ps,
- uint64_t mc_address_shader_vs,
- uint32_t ring_id)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle bo_dst, bo_cmd, resources[4];
- volatile unsigned char *ptr_dst;
- uint32_t *ptr_cmd;
- uint64_t mc_address_dst, mc_address_cmd;
- amdgpu_va_handle va_dst, va_cmd;
- int i, r;
- int bo_dst_size = 16384;
- int bo_cmd_size = 4096;
- struct amdgpu_cs_request ibs_request = {0};
- struct amdgpu_cs_ib_info ib_info = {0};
- struct amdgpu_cs_fence fence_status = {0};
- uint32_t expired;
- amdgpu_bo_list_handle bo_list;
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &bo_cmd, (void **)&ptr_cmd,
- &mc_address_cmd, &va_cmd);
- CU_ASSERT_EQUAL(r, 0);
- memset(ptr_cmd, 0, bo_cmd_size);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_dst, (void **)&ptr_dst,
- &mc_address_dst, &va_dst);
- CU_ASSERT_EQUAL(r, 0);
-
- i = 0;
- i += amdgpu_draw_init(ptr_cmd + i);
-
- i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst);
-
- i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i);
-
- i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_vs);
-
- i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_CONST, mc_address_shader_ps);
-
- ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0xc;
- ptr_cmd[i++] = 0x33333333;
- ptr_cmd[i++] = 0x33333333;
- ptr_cmd[i++] = 0x33333333;
- ptr_cmd[i++] = 0x33333333;
-
- i += amdgpu_draw_draw(ptr_cmd + i);
-
- while (i & 7)
- ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
-
- resources[0] = bo_dst;
- resources[1] = bo_shader_ps;
- resources[2] = bo_shader_vs;
- resources[3] = bo_cmd;
- r = amdgpu_bo_list_create(device_handle, 3, resources, NULL, &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ib_info.ib_mc_address = mc_address_cmd;
- ib_info.size = i;
- ibs_request.ip_type = AMDGPU_HW_IP_GFX;
- ibs_request.ring = ring_id;
- ibs_request.resources = bo_list;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.fence_info.handle = NULL;
-
- /* submit CS */
- r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
- fence_status.ip_instance = 0;
- fence_status.ring = ring_id;
- fence_status.context = context_handle;
- fence_status.fence = ibs_request.seq_no;
-
- /* wait for IB accomplished */
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,
- 0, &expired);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(expired, true);
-
- /* verify if memset test result meets with expected */
- i = 0;
- while(i < bo_dst_size) {
- CU_ASSERT_EQUAL(ptr_dst[i++], 0x33);
- }
-
- r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
- uint32_t ring)
-{
- amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
- void *ptr_shader_ps;
- void *ptr_shader_vs;
- uint64_t mc_address_shader_ps, mc_address_shader_vs;
- amdgpu_va_handle va_shader_ps, va_shader_vs;
- int r;
- int bo_shader_size = 4096;
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader_ps, &ptr_shader_ps,
- &mc_address_shader_ps, &va_shader_ps);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader_vs, &ptr_shader_vs,
- &mc_address_shader_vs, &va_shader_vs);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
- CU_ASSERT_EQUAL(r, 0);
-
- amdgpu_memset_draw(device_handle, bo_shader_ps, bo_shader_vs,
- mc_address_shader_ps, mc_address_shader_vs, ring);
-
- r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
- amdgpu_bo_handle bo_shader_ps,
- amdgpu_bo_handle bo_shader_vs,
- uint64_t mc_address_shader_ps,
- uint64_t mc_address_shader_vs,
- uint32_t ring)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle bo_dst, bo_src, bo_cmd, resources[5];
- volatile unsigned char *ptr_dst;
- unsigned char *ptr_src;
- uint32_t *ptr_cmd;
- uint64_t mc_address_dst, mc_address_src, mc_address_cmd;
- amdgpu_va_handle va_dst, va_src, va_cmd;
- int i, r;
- int bo_size = 16384;
- int bo_cmd_size = 4096;
- struct amdgpu_cs_request ibs_request = {0};
- struct amdgpu_cs_ib_info ib_info= {0};
- uint32_t hang_state, hangs, expired;
- amdgpu_bo_list_handle bo_list;
- struct amdgpu_cs_fence fence_status = {0};
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &bo_cmd, (void **)&ptr_cmd,
- &mc_address_cmd, &va_cmd);
- CU_ASSERT_EQUAL(r, 0);
- memset(ptr_cmd, 0, bo_cmd_size);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_src, (void **)&ptr_src,
- &mc_address_src, &va_src);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_dst, (void **)&ptr_dst,
- &mc_address_dst, &va_dst);
- CU_ASSERT_EQUAL(r, 0);
-
- memset(ptr_src, 0x55, bo_size);
-
- i = 0;
- i += amdgpu_draw_init(ptr_cmd + i);
-
- i += amdgpu_draw_setup_and_write_drawblt_surf_info(ptr_cmd + i, mc_address_dst);
-
- i += amdgpu_draw_setup_and_write_drawblt_state(ptr_cmd + i);
-
- i += amdgpu_draw_vs_RectPosTexFast_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_vs);
-
- i += amdgpu_draw_ps_write2hw(ptr_cmd + i, PS_TEX, mc_address_shader_ps);
-
- ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 8);
- ptr_cmd[i++] = 0xc;
- ptr_cmd[i++] = mc_address_src >> 8;
- ptr_cmd[i++] = mc_address_src >> 40 | 0x10e00000;
- ptr_cmd[i++] = 0x7c01f;
- ptr_cmd[i++] = 0x90500fac;
- ptr_cmd[i++] = 0x3e000;
- i += 3;
-
- ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 4);
- ptr_cmd[i++] = 0x14;
- ptr_cmd[i++] = 0x92;
- i += 3;
-
- ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
- ptr_cmd[i++] = 0x191;
- ptr_cmd[i++] = 0;
-
- i += amdgpu_draw_draw(ptr_cmd + i);
-
- while (i & 7)
- ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
-
- resources[0] = bo_dst;
- resources[1] = bo_src;
- resources[2] = bo_shader_ps;
- resources[3] = bo_shader_vs;
- resources[4] = bo_cmd;
- r = amdgpu_bo_list_create(device_handle, 5, resources, NULL, &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ib_info.ib_mc_address = mc_address_cmd;
- ib_info.size = i;
- ibs_request.ip_type = AMDGPU_HW_IP_GFX;
- ibs_request.ring = ring;
- ibs_request.resources = bo_list;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.fence_info.handle = NULL;
- r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
- CU_ASSERT_EQUAL(r, 0);
-
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
- fence_status.ip_instance = 0;
- fence_status.ring = ring;
- fence_status.context = context_handle;
- fence_status.fence = ibs_request.seq_no;
-
- /* wait for IB accomplished */
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,
- 0, &expired);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(expired, true);
-
- /* verify if memcpy test result meets with expected */
- i = 0;
- while(i < bo_size) {
- CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]);
- i++;
- }
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_size);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle, uint32_t ring)
-{
- amdgpu_bo_handle bo_shader_ps, bo_shader_vs;
- void *ptr_shader_ps;
- void *ptr_shader_vs;
- uint64_t mc_address_shader_ps, mc_address_shader_vs;
- amdgpu_va_handle va_shader_ps, va_shader_vs;
- int bo_shader_size = 4096;
- int r;
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader_ps, &ptr_shader_ps,
- &mc_address_shader_ps, &va_shader_ps);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
- AMDGPU_GEM_DOMAIN_VRAM, 0,
- &bo_shader_vs, &ptr_shader_vs,
- &mc_address_shader_vs, &va_shader_vs);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_draw_load_vs_shader(ptr_shader_vs);
- CU_ASSERT_EQUAL(r, 0);
-
- amdgpu_memcpy_draw(device_handle, bo_shader_ps, bo_shader_vs,
- mc_address_shader_ps, mc_address_shader_vs, ring);
-
- r = amdgpu_bo_unmap_and_free(bo_shader_ps, va_shader_ps, mc_address_shader_ps, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(bo_shader_vs, va_shader_vs, mc_address_shader_vs, bo_shader_size);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_draw_test(void)
-{
- int r;
- struct drm_amdgpu_info_hw_ip info;
- uint32_t ring_id;
-
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
- CU_ASSERT_EQUAL(r, 0);
-
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- amdgpu_memset_draw_test(device_handle, ring_id);
- amdgpu_memcpy_draw_test(device_handle, ring_id);
- }
-}
diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c
index 7cff4cf..9d4da4a 100644
--- a/tests/amdgpu/bo_tests.c
+++ b/tests/amdgpu/bo_tests.c
@@ -27,7 +27,6 @@
#include "amdgpu_test.h"
#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
@@ -45,7 +44,6 @@
static void amdgpu_bo_map_unmap(void);
static void amdgpu_memory_alloc(void);
static void amdgpu_mem_fail_alloc(void);
-static void amdgpu_bo_find_by_cpu_mapping(void);
CU_TestInfo bo_tests[] = {
{ "Export/Import", amdgpu_bo_export_import },
@@ -53,7 +51,6 @@
{ "CPU map/unmap", amdgpu_bo_map_unmap },
{ "Memory alloc Test", amdgpu_memory_alloc },
{ "Memory fail alloc Test", amdgpu_mem_fail_alloc },
- { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping },
CU_TEST_INFO_NULL,
};
@@ -242,27 +239,6 @@
r = gpu_mem_free(bo, va_handle, bo_mc, 4096);
CU_ASSERT_EQUAL(r, 0);
-
- /* Test GDS */
- bo = gpu_mem_alloc(device_handle, 1024, 0,
- AMDGPU_GEM_DOMAIN_GDS, 0,
- NULL, NULL);
- r = gpu_mem_free(bo, NULL, 0, 4096);
- CU_ASSERT_EQUAL(r, 0);
-
- /* Test GWS */
- bo = gpu_mem_alloc(device_handle, 1, 0,
- AMDGPU_GEM_DOMAIN_GWS, 0,
- NULL, NULL);
- r = gpu_mem_free(bo, NULL, 0, 4096);
- CU_ASSERT_EQUAL(r, 0);
-
- /* Test OA */
- bo = gpu_mem_alloc(device_handle, 1, 0,
- AMDGPU_GEM_DOMAIN_OA, 0,
- NULL, NULL);
- r = gpu_mem_free(bo, NULL, 0, 4096);
- CU_ASSERT_EQUAL(r, 0);
}
static void amdgpu_mem_fail_alloc(void)
@@ -286,33 +262,3 @@
CU_ASSERT_EQUAL(r, 0);
}
}
-
-static void amdgpu_bo_find_by_cpu_mapping(void)
-{
- amdgpu_bo_handle bo_handle, find_bo_handle;
- amdgpu_va_handle va_handle;
- void *bo_cpu;
- uint64_t bo_mc_address;
- uint64_t offset;
- int r;
-
- r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &bo_handle, &bo_cpu,
- &bo_mc_address, &va_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_find_bo_by_cpu_mapping(device_handle,
- bo_cpu,
- 4096,
- &find_bo_handle,
- &offset);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(offset, 0);
- CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle);
-
- atomic_dec(&find_bo_handle->refcount, 1);
- r = amdgpu_bo_unmap_and_free(bo_handle, va_handle,
- bo_mc_address, 4096);
- CU_ASSERT_EQUAL(r, 0);
-}
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index 91368c1..1eb5761 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -73,32 +73,6 @@
* 1 - pfp
*/
-#define PACKET3_WRITE_DATA 0x37
-#define WRITE_DATA_DST_SEL(x) ((x) << 8)
- /* 0 - register
- * 1 - memory (sync - via GRBM)
- * 2 - gl2
- * 3 - gds
- * 4 - reserved
- * 5 - memory (async - direct)
- */
-#define WR_ONE_ADDR (1 << 16)
-#define WR_CONFIRM (1 << 20)
-#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
- /* 0 - LRU
- * 1 - Stream
- */
-#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
- /* 0 - me
- * 1 - pfp
- * 2 - ce
- */
-
-#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f
-
-#define SDMA_PKT_HEADER_OP(x) (x & 0xff)
-#define SDMA_OP_POLL_REGMEM 8
-
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
@@ -106,14 +80,9 @@
static pthread_t stress_thread;
static uint32_t *ptr;
-int use_uc_mtype = 0;
-
static void amdgpu_deadlock_helper(unsigned ip_type);
static void amdgpu_deadlock_gfx(void);
static void amdgpu_deadlock_compute(void);
-static void amdgpu_illegal_reg_access();
-static void amdgpu_illegal_mem_access();
-static void amdgpu_deadlock_sdma(void);
CU_BOOL suite_deadlock_tests_enable(void)
{
@@ -123,20 +92,12 @@
&minor_version, &device_handle))
return CU_FALSE;
- /*
- * Only enable for ASICs supporting GPU reset and for which it's enabled
- * by default (currently GFX8/9 dGPUS)
- */
- if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
- device_handle->info.family_id != AMDGPU_FAMILY_AI &&
- device_handle->info.family_id != AMDGPU_FAMILY_CI) {
- printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
+ if (device_handle->info.family_id == AMDGPU_FAMILY_AI ||
+ device_handle->info.family_id == AMDGPU_FAMILY_SI) {
+ printf("\n\nCurrently hangs the CP on this ASIC, deadlock suite disabled\n");
enable = CU_FALSE;
}
- if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
- use_uc_mtype = 1;
-
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
@@ -173,11 +134,8 @@
CU_TestInfo deadlock_tests[] = {
- { "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx },
- { "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute },
- { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma },
- { "illegal reg access test", amdgpu_illegal_reg_access },
- { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access },
+ { "gfx ring block test", amdgpu_deadlock_gfx },
+ { "compute ring block test", amdgpu_deadlock_compute },
CU_TEST_INFO_NULL,
};
@@ -224,8 +182,8 @@
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
+ r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+ AMDGPU_GEM_DOMAIN_GTT, 0,
&ib_result_handle, &ib_result_cpu,
&ib_result_mc_address, &va_handle);
CU_ASSERT_EQUAL(r, 0);
@@ -265,6 +223,7 @@
ibs_request.ibs = &ib_info;
ibs_request.resources = bo_list;
ibs_request.fence_info.handle = NULL;
+
for (i = 0; i < 200; i++) {
r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
@@ -294,187 +253,3 @@
r = amdgpu_cs_ctx_free(context_handle);
CU_ASSERT_EQUAL(r, 0);
}
-
-static void amdgpu_deadlock_sdma(void)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle ib_result_handle;
- void *ib_result_cpu;
- uint64_t ib_result_mc_address;
- struct amdgpu_cs_request ibs_request;
- struct amdgpu_cs_ib_info ib_info;
- struct amdgpu_cs_fence fence_status;
- uint32_t expired;
- int i, r;
- amdgpu_bo_list_handle bo_list;
- amdgpu_va_handle va_handle;
- struct drm_amdgpu_info_hw_ip info;
- uint32_t ring_id;
-
- r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &info);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
- r = pthread_create(&stress_thread, NULL, write_mem_address, NULL);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0,
- &ib_result_handle, &ib_result_cpu,
- &ib_result_mc_address, &va_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
- &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ptr = ib_result_cpu;
- i = 0;
-
- ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
- (0 << 26) | /* WAIT_REG_MEM */
- (4 << 28) | /* != */
- (1 << 31); /* memory */
- ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc;
- ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff;
- ptr[i++] = 0x00000000; /* reference value */
- ptr[i++] = 0xffffffff; /* and mask */
- ptr[i++] = 4 | /* poll interval */
- (0xfff << 16); /* retry count */
-
- for (; i < 16; i++)
- ptr[i] = 0;
-
- ptr[256] = 0x0; /* the memory we wait on to change */
-
- memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
- ib_info.ib_mc_address = ib_result_mc_address;
- ib_info.size = 16;
-
- memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
- ibs_request.ip_type = AMDGPU_HW_IP_DMA;
- ibs_request.ring = ring_id;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.resources = bo_list;
- ibs_request.fence_info.handle = NULL;
-
- for (i = 0; i < 200; i++) {
- r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
- CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
- }
-
- memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
- fence_status.context = context_handle;
- fence_status.ip_type = AMDGPU_HW_IP_DMA;
- fence_status.ip_instance = 0;
- fence_status.ring = ring_id;
- fence_status.fence = ibs_request.seq_no;
-
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,0, &expired);
- CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
- pthread_join(stress_thread, NULL);
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
- ib_result_mc_address, 4096);
- CU_ASSERT_EQUAL(r, 0);
- }
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void bad_access_helper(int reg_access)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle ib_result_handle;
- void *ib_result_cpu;
- uint64_t ib_result_mc_address;
- struct amdgpu_cs_request ibs_request;
- struct amdgpu_cs_ib_info ib_info;
- struct amdgpu_cs_fence fence_status;
- uint32_t expired;
- int i, r;
- amdgpu_bo_list_handle bo_list;
- amdgpu_va_handle va_handle;
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0, 0,
- &ib_result_handle, &ib_result_cpu,
- &ib_result_mc_address, &va_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
- &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ptr = ib_result_cpu;
- i = 0;
-
- ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3);
- ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM;
- ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0;
- ptr[i++] = 0;
- ptr[i++] = 0xdeadbeef;
-
- for (; i < 16; ++i)
- ptr[i] = 0xffff1000;
-
- memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
- ib_info.ib_mc_address = ib_result_mc_address;
- ib_info.size = 16;
-
- memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
- ibs_request.ip_type = AMDGPU_HW_IP_GFX;
- ibs_request.ring = 0;
- ibs_request.number_of_ibs = 1;
- ibs_request.ibs = &ib_info;
- ibs_request.resources = bo_list;
- ibs_request.fence_info.handle = NULL;
-
- r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
- CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
-
- memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
- fence_status.context = context_handle;
- fence_status.ip_type = AMDGPU_HW_IP_GFX;
- fence_status.ip_instance = 0;
- fence_status.ring = 0;
- fence_status.fence = ibs_request.seq_no;
-
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,0, &expired);
- CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1);
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
- ib_result_mc_address, 4096);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_illegal_reg_access()
-{
- bad_access_helper(1);
-}
-
-static void amdgpu_illegal_mem_access()
-{
- bad_access_helper(0);
-}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 1726cb4..4c1237c 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@
files(
'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
- 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
+ 'vm_tests.c',
),
dependencies : [dep_cunit, dep_threads],
include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/ras_tests.c b/tests/amdgpu/ras_tests.c
deleted file mode 100644
index 81c34ad..0000000
--- a/tests/amdgpu/ras_tests.c
+++ /dev/null
@@ -1,650 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include "CUnit/Basic.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include <unistd.h>
-#include <fcntl.h>
-#include <stdio.h>
-#include "xf86drm.h"
-
-const char *ras_block_string[] = {
- "umc",
- "sdma",
- "gfx",
- "mmhub",
- "athub",
- "pcie_bif",
- "hdp",
- "xgmi_wafl",
- "df",
- "smn",
- "sem",
- "mp0",
- "mp1",
- "fuse",
-};
-
-#define ras_block_str(i) (ras_block_string[i])
-
-enum amdgpu_ras_block {
- AMDGPU_RAS_BLOCK__UMC = 0,
- AMDGPU_RAS_BLOCK__SDMA,
- AMDGPU_RAS_BLOCK__GFX,
- AMDGPU_RAS_BLOCK__MMHUB,
- AMDGPU_RAS_BLOCK__ATHUB,
- AMDGPU_RAS_BLOCK__PCIE_BIF,
- AMDGPU_RAS_BLOCK__HDP,
- AMDGPU_RAS_BLOCK__XGMI_WAFL,
- AMDGPU_RAS_BLOCK__DF,
- AMDGPU_RAS_BLOCK__SMN,
- AMDGPU_RAS_BLOCK__SEM,
- AMDGPU_RAS_BLOCK__MP0,
- AMDGPU_RAS_BLOCK__MP1,
- AMDGPU_RAS_BLOCK__FUSE,
-
- AMDGPU_RAS_BLOCK__LAST
-};
-
-#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST
-#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
-
-enum amdgpu_ras_error_type {
- AMDGPU_RAS_ERROR__NONE = 0,
- AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2,
- AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4,
- AMDGPU_RAS_ERROR__POISON = 8,
-};
-
-struct ras_common_if {
- enum amdgpu_ras_block block;
- enum amdgpu_ras_error_type type;
- uint32_t sub_block_index;
- char name[32];
-};
-
-struct ras_inject_if {
- struct ras_common_if head;
- uint64_t address;
- uint64_t value;
-};
-
-struct ras_debug_if {
- union {
- struct ras_common_if head;
- struct ras_inject_if inject;
- };
- int op;
-};
-/* for now, only umc, gfx, sdma has implemented. */
-#define DEFAULT_RAS_BLOCK_MASK_INJECT (1 << AMDGPU_RAS_BLOCK__UMC)
-#define DEFAULT_RAS_BLOCK_MASK_QUERY (1 << AMDGPU_RAS_BLOCK__UMC)
-#define DEFAULT_RAS_BLOCK_MASK_BASIC (1 << AMDGPU_RAS_BLOCK__UMC |\
- (1 << AMDGPU_RAS_BLOCK__SDMA) |\
- (1 << AMDGPU_RAS_BLOCK__GFX))
-
-static uint32_t ras_block_mask_inject = DEFAULT_RAS_BLOCK_MASK_INJECT;
-static uint32_t ras_block_mask_query = DEFAULT_RAS_BLOCK_MASK_INJECT;
-static uint32_t ras_block_mask_basic = DEFAULT_RAS_BLOCK_MASK_BASIC;
-
-struct ras_test_mask {
- uint32_t inject_mask;
- uint32_t query_mask;
- uint32_t basic_mask;
-};
-
-struct amdgpu_ras_data {
- amdgpu_device_handle device_handle;
- uint32_t id;
- uint32_t capability;
- struct ras_test_mask test_mask;
-};
-
-/* all devices who has ras supported */
-static struct amdgpu_ras_data devices[MAX_CARDS_SUPPORTED];
-static int devices_count;
-
-struct ras_DID_test_mask{
- uint16_t device_id;
- uint16_t revision_id;
- struct ras_test_mask test_mask;
-};
-
-/* white list for inject test. */
-#define RAS_BLOCK_MASK_ALL {\
- DEFAULT_RAS_BLOCK_MASK_INJECT,\
- DEFAULT_RAS_BLOCK_MASK_QUERY,\
- DEFAULT_RAS_BLOCK_MASK_BASIC\
-}
-
-#define RAS_BLOCK_MASK_QUERY_BASIC {\
- 0,\
- DEFAULT_RAS_BLOCK_MASK_QUERY,\
- DEFAULT_RAS_BLOCK_MASK_BASIC\
-}
-
-static const struct ras_DID_test_mask ras_DID_array[] = {
- {0x66a1, 0x00, RAS_BLOCK_MASK_ALL},
- {0x66a1, 0x01, RAS_BLOCK_MASK_ALL},
- {0x66a1, 0x04, RAS_BLOCK_MASK_ALL},
-};
-
-static struct ras_test_mask amdgpu_ras_get_test_mask(drmDevicePtr device)
-{
- int i;
- static struct ras_test_mask default_test_mask = RAS_BLOCK_MASK_QUERY_BASIC;
-
- for (i = 0; i < sizeof(ras_DID_array) / sizeof(ras_DID_array[0]); i++) {
- if (ras_DID_array[i].device_id == device->deviceinfo.pci->device_id &&
- ras_DID_array[i].revision_id == device->deviceinfo.pci->revision_id)
- return ras_DID_array[i].test_mask;
- }
- return default_test_mask;
-}
-
-static uint32_t amdgpu_ras_lookup_capability(amdgpu_device_handle device_handle)
-{
- union {
- uint64_t feature_mask;
- struct {
- uint32_t enabled_features;
- uint32_t supported_features;
- };
- } features = { 0 };
- int ret;
-
- ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES,
- sizeof(features), &features);
- if (ret)
- return 0;
-
- return features.supported_features;
-}
-
-static int get_file_contents(char *file, char *buf, int size);
-
-static int amdgpu_ras_lookup_id(drmDevicePtr device)
-{
- char path[1024];
- char str[128];
- drmPciBusInfo info;
- int i;
- int ret;
-
- for (i = 0; i < MAX_CARDS_SUPPORTED; i++) {
- memset(str, 0, sizeof(str));
- memset(&info, 0, sizeof(info));
- sprintf(path, "/sys/kernel/debug/dri/%d/name", i);
- if (get_file_contents(path, str, sizeof(str)) <= 0)
- continue;
-
- ret = sscanf(str, "amdgpu dev=%04hx:%02hhx:%02hhx.%01hhx",
- &info.domain, &info.bus, &info.dev, &info.func);
- if (ret != 4)
- continue;
-
- if (memcmp(&info, device->businfo.pci, sizeof(info)) == 0)
- return i;
- }
- return -1;
-}
-
-CU_BOOL suite_ras_tests_enable(void)
-{
- amdgpu_device_handle device_handle;
- uint32_t major_version;
- uint32_t minor_version;
- int i;
- drmDevicePtr device;
-
- for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
- if (amdgpu_device_initialize(drm_amdgpu[i], &major_version,
- &minor_version, &device_handle))
- continue;
-
- if (drmGetDevice2(drm_amdgpu[i],
- DRM_DEVICE_GET_PCI_REVISION,
- &device))
- continue;
-
- if (device->bustype == DRM_BUS_PCI &&
- amdgpu_ras_lookup_capability(device_handle)) {
- amdgpu_device_deinitialize(device_handle);
- return CU_TRUE;
- }
-
- if (amdgpu_device_deinitialize(device_handle))
- continue;
- }
-
- return CU_FALSE;
-}
-
-int suite_ras_tests_init(void)
-{
- drmDevicePtr device;
- amdgpu_device_handle device_handle;
- uint32_t major_version;
- uint32_t minor_version;
- uint32_t capability;
- struct ras_test_mask test_mask;
- int id;
- int i;
- int r;
-
- for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) {
- r = amdgpu_device_initialize(drm_amdgpu[i], &major_version,
- &minor_version, &device_handle);
- if (r)
- continue;
-
- if (drmGetDevice2(drm_amdgpu[i],
- DRM_DEVICE_GET_PCI_REVISION,
- &device)) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- if (device->bustype != DRM_BUS_PCI) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- capability = amdgpu_ras_lookup_capability(device_handle);
- if (capability == 0) {
- amdgpu_device_deinitialize(device_handle);
- continue;
-
- }
-
- id = amdgpu_ras_lookup_id(device);
- if (id == -1) {
- amdgpu_device_deinitialize(device_handle);
- continue;
- }
-
- test_mask = amdgpu_ras_get_test_mask(device);
-
- devices[devices_count++] = (struct amdgpu_ras_data) {
- device_handle, id, capability, test_mask,
- };
- }
-
- if (devices_count == 0)
- return CUE_SINIT_FAILED;
-
- return CUE_SUCCESS;
-}
-
-int suite_ras_tests_clean(void)
-{
- int r;
- int i;
- int ret = CUE_SUCCESS;
-
- for (i = 0; i < devices_count; i++) {
- r = amdgpu_device_deinitialize(devices[i].device_handle);
- if (r)
- ret = CUE_SCLEAN_FAILED;
- }
- return ret;
-}
-
-static void amdgpu_ras_disable_test(void);
-static void amdgpu_ras_enable_test(void);
-static void amdgpu_ras_inject_test(void);
-static void amdgpu_ras_query_test(void);
-static void amdgpu_ras_basic_test(void);
-
-CU_TestInfo ras_tests[] = {
- { "ras basic test", amdgpu_ras_basic_test },
- { "ras query test", amdgpu_ras_query_test },
- { "ras inject test", amdgpu_ras_inject_test },
- { "ras disable test", amdgpu_ras_disable_test },
-#if 0
- { "ras enable test", amdgpu_ras_enable_test },
-#endif
- CU_TEST_INFO_NULL,
-};
-
-//helpers
-
-static int test_card;
-static char sysfs_path[1024];
-static char debugfs_path[1024];
-static uint32_t ras_mask;
-static amdgpu_device_handle device_handle;
-
-static int set_test_card(int card)
-{
- int i;
-
- test_card = card;
- sprintf(sysfs_path, "/sys/class/drm/card%d/device/ras/", devices[card].id);
- sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/ras/", devices[card].id);
- ras_mask = devices[card].capability;
- device_handle = devices[card].device_handle;
- ras_block_mask_inject = devices[card].test_mask.inject_mask;
- ras_block_mask_query = devices[card].test_mask.query_mask;
- ras_block_mask_basic = devices[card].test_mask.basic_mask;
-
- return 0;
-}
-
-static const char *get_ras_sysfs_root(void)
-{
- return sysfs_path;
-}
-
-static const char *get_ras_debugfs_root(void)
-{
- return debugfs_path;
-}
-
-static int set_file_contents(char *file, char *buf, int size)
-{
- int n, fd;
- fd = open(file, O_WRONLY);
- if (fd == -1)
- return -1;
- n = write(fd, buf, size);
- close(fd);
- return n;
-}
-
-static int get_file_contents(char *file, char *buf, int size)
-{
- int n, fd;
- fd = open(file, O_RDONLY);
- if (fd == -1)
- return -1;
- n = read(fd, buf, size);
- close(fd);
- return n;
-}
-
-static int is_file_ok(char *file, int flags)
-{
- int fd;
-
- fd = open(file, flags);
- if (fd == -1)
- return -1;
- close(fd);
- return 0;
-}
-
-static int amdgpu_ras_is_feature_enabled(enum amdgpu_ras_block block)
-{
- uint32_t feature_mask;
- int ret;
-
- ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES,
- sizeof(feature_mask), &feature_mask);
- if (ret)
- return -1;
-
- return (1 << block) & feature_mask;
-}
-
-static int amdgpu_ras_is_feature_supported(enum amdgpu_ras_block block)
-{
- return (1 << block) & ras_mask;
-}
-
-static int amdgpu_ras_invoke(struct ras_debug_if *data)
-{
- char path[1024];
- int ret;
-
- sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
-
- ret = set_file_contents(path, (char *)data, sizeof(*data))
- - sizeof(*data);
- return ret;
-}
-
-static int amdgpu_ras_query_err_count(enum amdgpu_ras_block block,
- unsigned long *ue, unsigned long *ce)
-{
- char buf[64];
- char name[1024];
- int ret;
-
- *ue = *ce = 0;
-
- if (amdgpu_ras_is_feature_supported(block) <= 0)
- return -1;
-
- sprintf(name, "%s%s%s", get_ras_sysfs_root(), ras_block_str(block), "_err_count");
-
- if (is_file_ok(name, O_RDONLY))
- return 0;
-
- if (get_file_contents(name, buf, sizeof(buf)) <= 0)
- return -1;
-
- if (sscanf(buf, "ue: %lu\nce: %lu", ue, ce) != 2)
- return -1;
-
- return 0;
-}
-
-//tests
-static void amdgpu_ras_features_test(int enable)
-{
- struct ras_debug_if data;
- int ret;
- int i;
-
- data.op = enable;
- for (i = 0; i < AMDGPU_RAS_BLOCK__LAST; i++) {
- struct ras_common_if head = {
- .block = i,
- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
- .sub_block_index = 0,
- .name = "",
- };
-
- if (amdgpu_ras_is_feature_supported(i) <= 0)
- continue;
-
- data.head = head;
-
- ret = amdgpu_ras_invoke(&data);
- CU_ASSERT_EQUAL(ret, 0);
-
- if (ret)
- continue;
-
- ret = enable ^ amdgpu_ras_is_feature_enabled(i);
- CU_ASSERT_EQUAL(ret, 0);
- }
-}
-
-static void amdgpu_ras_disable_test(void)
-{
- int i;
- for (i = 0; i < devices_count; i++) {
- set_test_card(i);
- amdgpu_ras_features_test(0);
- }
-}
-
-static void amdgpu_ras_enable_test(void)
-{
- int i;
- for (i = 0; i < devices_count; i++) {
- set_test_card(i);
- amdgpu_ras_features_test(1);
- }
-}
-
-static void __amdgpu_ras_inject_test(void)
-{
- struct ras_debug_if data;
- int ret;
- int i;
- unsigned long ue, ce, ue_old, ce_old;
-
- data.op = 2;
- for (i = 0; i < AMDGPU_RAS_BLOCK__LAST; i++) {
- int timeout = 3;
- struct ras_inject_if inject = {
- .head = {
- .block = i,
- .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
- .sub_block_index = 0,
- .name = "",
- },
- .address = 0,
- .value = 0,
- };
-
- if (amdgpu_ras_is_feature_enabled(i) <= 0)
- continue;
-
- if (!((1 << i) & ras_block_mask_inject))
- continue;
-
- data.inject = inject;
-
- ret = amdgpu_ras_query_err_count(i, &ue_old, &ce_old);
- CU_ASSERT_EQUAL(ret, 0);
-
- if (ret)
- continue;
-
- ret = amdgpu_ras_invoke(&data);
- CU_ASSERT_EQUAL(ret, 0);
-
- if (ret)
- continue;
-
-loop:
- while (timeout > 0) {
- ret = amdgpu_ras_query_err_count(i, &ue, &ce);
- CU_ASSERT_EQUAL(ret, 0);
-
- if (ret)
- continue;
- if (ue_old != ue) {
- /*recovery takes ~10s*/
- sleep(10);
- break;
- }
-
- sleep(1);
- timeout -= 1;
- }
-
- CU_ASSERT_EQUAL(ue_old + 1, ue);
- CU_ASSERT_EQUAL(ce_old, ce);
- }
-}
-
-static void amdgpu_ras_inject_test(void)
-{
- int i;
- for (i = 0; i < devices_count; i++) {
- set_test_card(i);
- __amdgpu_ras_inject_test();
- }
-}
-
-static void __amdgpu_ras_query_test(void)
-{
- unsigned long ue, ce;
- int ret;
- int i;
-
- for (i = 0; i < AMDGPU_RAS_BLOCK__LAST; i++) {
- if (amdgpu_ras_is_feature_supported(i) <= 0)
- continue;
-
- if (!((1 << i) & ras_block_mask_query))
- continue;
-
- ret = amdgpu_ras_query_err_count(i, &ue, &ce);
- CU_ASSERT_EQUAL(ret, 0);
- }
-}
-
-static void amdgpu_ras_query_test(void)
-{
- int i;
- for (i = 0; i < devices_count; i++) {
- set_test_card(i);
- __amdgpu_ras_query_test();
- }
-}
-
-static void amdgpu_ras_basic_test(void)
-{
- unsigned long ue, ce;
- char name[1024];
- int ret;
- int i;
- int j;
- uint32_t features;
- char path[1024];
-
- ret = is_file_ok("/sys/module/amdgpu/parameters/ras_mask", O_RDONLY);
- CU_ASSERT_EQUAL(ret, 0);
-
- for (i = 0; i < devices_count; i++) {
- set_test_card(i);
-
- ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES,
- sizeof(features), &features);
- CU_ASSERT_EQUAL(ret, 0);
-
- sprintf(path, "%s%s", get_ras_debugfs_root(), "ras_ctrl");
- ret = is_file_ok(path, O_WRONLY);
- CU_ASSERT_EQUAL(ret, 0);
-
- sprintf(path, "%s%s", get_ras_sysfs_root(), "features");
- ret = is_file_ok(path, O_RDONLY);
- CU_ASSERT_EQUAL(ret, 0);
-
- for (j = 0; j < AMDGPU_RAS_BLOCK__LAST; j++) {
- ret = amdgpu_ras_is_feature_supported(j);
- if (ret <= 0)
- continue;
-
- if (!((1 << j) & ras_block_mask_basic))
- continue;
-
- sprintf(path, "%s%s%s", get_ras_sysfs_root(), ras_block_str(j), "_err_count");
- ret = is_file_ok(path, O_RDONLY);
- CU_ASSERT_EQUAL(ret, 0);
-
- sprintf(path, "%s%s%s", get_ras_debugfs_root(), ras_block_str(j), "_err_inject");
- ret = is_file_ok(path, O_WRONLY);
- CU_ASSERT_EQUAL(ret, 0);
- }
- }
-}
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
deleted file mode 100644
index 869ed88..0000000
--- a/tests/amdgpu/syncobj_tests.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * Copyright 2017 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
-*/
-
-#include "CUnit/Basic.h"
-#include "xf86drm.h"
-
-#include "amdgpu_test.h"
-#include "amdgpu_drm.h"
-#include "amdgpu_internal.h"
-#include <pthread.h>
-
-static amdgpu_device_handle device_handle;
-static uint32_t major_version;
-static uint32_t minor_version;
-
-static void amdgpu_syncobj_timeline_test(void);
-
-CU_BOOL suite_syncobj_timeline_tests_enable(void)
-{
- int r;
- uint64_t cap = 0;
-
- r = drmGetCap(drm_amdgpu[0], DRM_CAP_SYNCOBJ_TIMELINE, &cap);
- if (r || cap == 0)
- return CU_FALSE;
-
- return CU_TRUE;
-}
-
-int suite_syncobj_timeline_tests_init(void)
-{
- int r;
-
- r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
- &minor_version, &device_handle);
-
- if (r) {
- if ((r == -EACCES) && (errno == EACCES))
- printf("\n\nError:%s. "
- "Hint:Try to run this test program as root.",
- strerror(errno));
- return CUE_SINIT_FAILED;
- }
-
- return CUE_SUCCESS;
-}
-
-int suite_syncobj_timeline_tests_clean(void)
-{
- int r = amdgpu_device_deinitialize(device_handle);
-
- if (r == 0)
- return CUE_SUCCESS;
- else
- return CUE_SCLEAN_FAILED;
-}
-
-
-CU_TestInfo syncobj_timeline_tests[] = {
- { "syncobj timeline test", amdgpu_syncobj_timeline_test },
- CU_TEST_INFO_NULL,
-};
-
-#define GFX_COMPUTE_NOP 0xffff1000
-#define SDMA_NOP 0x0
-static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
- wait_or_signal, uint64_t point)
-{
- amdgpu_context_handle context_handle;
- amdgpu_bo_handle ib_result_handle;
- void *ib_result_cpu;
- uint64_t ib_result_mc_address;
- struct drm_amdgpu_cs_chunk chunks[2];
- struct drm_amdgpu_cs_chunk_data chunk_data;
- struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
- struct amdgpu_cs_fence fence_status;
- amdgpu_bo_list_handle bo_list;
- amdgpu_va_handle va_handle;
- uint32_t expired, flags;
- int i, r;
- uint64_t seq_no;
- static uint32_t *ptr;
-
- r = amdgpu_cs_ctx_create(device_handle, &context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
- AMDGPU_GEM_DOMAIN_GTT, 0,
- &ib_result_handle, &ib_result_cpu,
- &ib_result_mc_address, &va_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
- &bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- ptr = ib_result_cpu;
-
- for (i = 0; i < 16; ++i)
- ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
-
- chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
- chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
- chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
- chunk_data.ib_data._pad = 0;
- chunk_data.ib_data.va_start = ib_result_mc_address;
- chunk_data.ib_data.ib_bytes = 16 * 4;
- chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
- AMDGPU_HW_IP_DMA;
- chunk_data.ib_data.ip_instance = 0;
- chunk_data.ib_data.ring = 0;
- chunk_data.ib_data.flags = 0;
-
- chunks[1].chunk_id = wait_or_signal ?
- AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
- AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
- chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
- chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
- syncobj_data.handle = syncobj_handle;
- syncobj_data.point = point;
- syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
-
- r = amdgpu_cs_submit_raw(device_handle,
- context_handle,
- bo_list,
- 2,
- chunks,
- &seq_no);
- CU_ASSERT_EQUAL(r, 0);
-
-
- memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
- fence_status.context = context_handle;
- fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
- AMDGPU_HW_IP_DMA;
- fence_status.ip_instance = 0;
- fence_status.ring = 0;
- fence_status.fence = seq_no;
-
- r = amdgpu_cs_query_fence_status(&fence_status,
- AMDGPU_TIMEOUT_INFINITE,0, &expired);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_list_destroy(bo_list);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
- ib_result_mc_address, 4096);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_cs_ctx_free(context_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- return r;
-}
-
-struct syncobj_point {
- uint32_t syncobj_handle;
- uint64_t point;
-};
-
-static void *syncobj_wait(void *data)
-{
- struct syncobj_point *sp = (struct syncobj_point *)data;
- int r;
-
- r = syncobj_command_submission_helper(sp->syncobj_handle, true,
- sp->point);
- CU_ASSERT_EQUAL(r, 0);
-
- return (void *)(long)r;
-}
-
-static void *syncobj_signal(void *data)
-{
- struct syncobj_point *sp = (struct syncobj_point *)data;
- int r;
-
- r = syncobj_command_submission_helper(sp->syncobj_handle, false,
- sp->point);
- CU_ASSERT_EQUAL(r, 0);
-
- return (void *)(long)r;
-}
-
-static void amdgpu_syncobj_timeline_test(void)
-{
- static pthread_t wait_thread;
- static pthread_t signal_thread;
- static pthread_t c_thread;
- struct syncobj_point sp1, sp2, sp3;
- uint32_t syncobj_handle;
- uint64_t payload;
- uint64_t wait_point, signal_point;
- uint64_t timeout;
- struct timespec tp;
- int r, sync_fd;
- void *tmp;
-
- r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
- CU_ASSERT_EQUAL(r, 0);
-
- // wait on point 5
- sp1.syncobj_handle = syncobj_handle;
- sp1.point = 5;
- r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
- CU_ASSERT_EQUAL(r, 0);
-
- // signal on point 10
- sp2.syncobj_handle = syncobj_handle;
- sp2.point = 10;
- r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
- CU_ASSERT_EQUAL(r, 0);
-
- r = pthread_join(wait_thread, &tmp);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(tmp, 0);
-
- r = pthread_join(signal_thread, &tmp);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(tmp, 0);
-
- //query timeline payload
- r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
- &payload, 1);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(payload, 10);
-
- //signal on point 16
- sp3.syncobj_handle = syncobj_handle;
- sp3.point = 16;
- r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
- CU_ASSERT_EQUAL(r, 0);
- //CPU wait on point 16
- wait_point = 16;
- timeout = 0;
- clock_gettime(CLOCK_MONOTONIC, &tp);
- timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
- timeout += 0x10000000000; //10s
- r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
- &wait_point, 1, timeout,
- DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
- DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
- NULL);
-
- CU_ASSERT_EQUAL(r, 0);
- r = pthread_join(c_thread, &tmp);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(tmp, 0);
-
- // export point 16 and import to point 18
- r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
- 16,
- DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
- &sync_fd);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
- 18, sync_fd);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
- &payload, 1);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(payload, 18);
-
- // CPU signal on point 20
- signal_point = 20;
- r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
- &signal_point, 1);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
- &payload, 1);
- CU_ASSERT_EQUAL(r, 0);
- CU_ASSERT_EQUAL(payload, 20);
-
- r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
- CU_ASSERT_EQUAL(r, 0);
-
-}
diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
index f3108a0..80ab179 100644
--- a/tests/amdgpu/vce_ib.h
+++ b/tests/amdgpu/vce_ib.h
@@ -315,21 +315,4 @@
0x00000008,
0x02000001,
};
-
-static const uint32_t vce_mv_buffer[] = {
- 0x00000038,
- 0x0500000d,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
#endif /*_vce_ib_h*/
diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c
index 0026826..25c0b1f 100644
--- a/tests/amdgpu/vce_tests.c
+++ b/tests/amdgpu/vce_tests.c
@@ -37,7 +37,6 @@
#define IB_SIZE 4096
#define MAX_RESOURCES 16
-#define FW_53_0_03 ((53 << 24) | (0 << 16) | (03 << 8))
struct amdgpu_vce_bo {
amdgpu_bo_handle handle;
@@ -56,9 +55,6 @@
struct amdgpu_vce_bo cpb;
unsigned ib_len;
bool two_instance;
- struct amdgpu_vce_bo mvrefbuf;
- struct amdgpu_vce_bo mvb;
- unsigned mvbuf_size;
};
static amdgpu_device_handle device_handle;
@@ -66,10 +62,6 @@
static uint32_t minor_version;
static uint32_t family_id;
static uint32_t vce_harvest_config;
-static uint32_t chip_rev;
-static uint32_t chip_id;
-static uint32_t ids_flags;
-static bool is_mv_supported = true;
static amdgpu_context_handle context_handle;
static amdgpu_bo_handle ib_handle;
@@ -83,58 +75,33 @@
static void amdgpu_cs_vce_create(void);
static void amdgpu_cs_vce_encode(void);
-static void amdgpu_cs_vce_encode_mv(void);
static void amdgpu_cs_vce_destroy(void);
CU_TestInfo vce_tests[] = {
{ "VCE create", amdgpu_cs_vce_create },
{ "VCE encode", amdgpu_cs_vce_encode },
- { "VCE MV dump", amdgpu_cs_vce_encode_mv },
{ "VCE destroy", amdgpu_cs_vce_destroy },
CU_TEST_INFO_NULL,
};
+
CU_BOOL suite_vce_tests_enable(void)
{
- uint32_t version, feature;
- CU_BOOL ret_mv = CU_FALSE;
-
if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
&minor_version, &device_handle))
return CU_FALSE;
family_id = device_handle->info.family_id;
- chip_rev = device_handle->info.chip_rev;
- chip_id = device_handle->info.chip_external_rev;
- ids_flags = device_handle->info.ids_flags;
-
- amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0,
- 0, &version, &feature);
if (amdgpu_device_deinitialize(device_handle))
return CU_FALSE;
+
if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) {
printf("\n\nThe ASIC NOT support VCE, suite disabled\n");
return CU_FALSE;
}
- if (!(chip_id == (chip_rev + 0x3C) || /* FIJI */
- chip_id == (chip_rev + 0x50) || /* Polaris 10*/
- chip_id == (chip_rev + 0x5A) || /* Polaris 11*/
- chip_id == (chip_rev + 0x64) || /* Polaris 12*/
- (family_id >= AMDGPU_FAMILY_AI && !ids_flags))) /* dGPU > Polaris */
- printf("\n\nThe ASIC NOT support VCE MV, suite disabled\n");
- else if (FW_53_0_03 > version)
- printf("\n\nThe ASIC FW version NOT support VCE MV, suite disabled\n");
- else
- ret_mv = CU_TRUE;
-
- if (ret_mv == CU_FALSE) {
- amdgpu_set_test_active("VCE Tests", "VCE MV dump", ret_mv);
- is_mv_supported = false;
- }
-
return CU_TRUE;
}
@@ -303,12 +270,6 @@
memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
ib_cpu[len + 8] = ALIGN(enc.width, align);
ib_cpu[len + 9] = ALIGN(enc.width, align);
- if (is_mv_supported == true) {/* disableTwoInstance */
- if (family_id >= AMDGPU_FAMILY_AI)
- ib_cpu[len + 11] = 0x01000001;
- else
- ib_cpu[len + 11] = 0x01000201;
- }
len += sizeof(vce_create) / 4;
memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
ib_cpu[len + 2] = enc.fb[0].addr >> 32;
@@ -340,15 +301,13 @@
memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
len += sizeof(vce_rdo) / 4;
memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
- if (is_mv_supported == true)
- ib_cpu[len + 27] = 0x00000001; /* encSliceMode */
len += sizeof(vce_pic_ctrl) / 4;
r = submit(len, AMDGPU_HW_IP_VCE);
CU_ASSERT_EQUAL(r, 0);
}
-static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
+static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc)
{
uint64_t luma_offset, chroma_offset;
@@ -562,178 +521,6 @@
free_resource(&enc.cpb);
}
-static void amdgpu_cs_vce_mv(struct amdgpu_vce_encode *enc)
-{
- uint64_t luma_offset, chroma_offset;
- uint64_t mv_ref_luma_offset;
- unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
- unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16);
- int len = 0, i, r;
-
- luma_offset = enc->vbuf.addr;
- chroma_offset = luma_offset + luma_size;
- mv_ref_luma_offset = enc->mvrefbuf.addr;
-
- memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
- len += sizeof(vce_session) / 4;
- memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
- len += sizeof(vce_taskinfo) / 4;
- memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
- ib_cpu[len + 2] = enc->bs[0].addr >> 32;
- ib_cpu[len + 3] = enc->bs[0].addr;
- len += sizeof(vce_bs_buffer) / 4;
- memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer));
- ib_cpu[len + 2] = enc->cpb.addr >> 32;
- ib_cpu[len + 3] = enc->cpb.addr;
- len += sizeof(vce_context_buffer) / 4;
- memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
- for (i = 0; i < 8; ++i)
- ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
- for (i = 0; i < 8; ++i)
- ib_cpu[len + 10 + i] = luma_size * 1.5;
- len += sizeof(vce_aux_buffer) / 4;
- memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
- ib_cpu[len + 2] = enc->fb[0].addr >> 32;
- ib_cpu[len + 3] = enc->fb[0].addr;
- len += sizeof(vce_feedback) / 4;
- memcpy((ib_cpu + len), vce_mv_buffer, sizeof(vce_mv_buffer));
- ib_cpu[len + 2] = mv_ref_luma_offset >> 32;
- ib_cpu[len + 3] = mv_ref_luma_offset;
- ib_cpu[len + 4] = ALIGN(enc->width, align);
- ib_cpu[len + 5] = ALIGN(enc->width, align);
- ib_cpu[len + 6] = luma_size;
- ib_cpu[len + 7] = enc->mvb.addr >> 32;
- ib_cpu[len + 8] = enc->mvb.addr;
- len += sizeof(vce_mv_buffer) / 4;
- memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
- ib_cpu[len + 2] = 0;
- ib_cpu[len + 3] = 0;
- ib_cpu[len + 4] = 0x154000;
- ib_cpu[len + 9] = luma_offset >> 32;
- ib_cpu[len + 10] = luma_offset;
- ib_cpu[len + 11] = chroma_offset >> 32;
- ib_cpu[len + 12] = chroma_offset;
- ib_cpu[len + 13] = ALIGN(enc->height, 16);;
- ib_cpu[len + 14] = ALIGN(enc->width, align);
- ib_cpu[len + 15] = ALIGN(enc->width, align);
- /* encDisableMBOffloading-encDisableTwoPipeMode-encInputPicArrayMode-encInputPicAddrMode */
- ib_cpu[len + 16] = 0x01010000;
- ib_cpu[len + 18] = 0; /* encPicType */
- ib_cpu[len + 19] = 0; /* encIdrFlag */
- ib_cpu[len + 20] = 0; /* encIdrPicId */
- ib_cpu[len + 21] = 0; /* encMGSKeyPic */
- ib_cpu[len + 22] = 0; /* encReferenceFlag */
- ib_cpu[len + 23] = 0; /* encTemporalLayerIndex */
- ib_cpu[len + 55] = 0; /* pictureStructure */
- ib_cpu[len + 56] = 0; /* encPicType -ref[0] */
- ib_cpu[len + 61] = 0; /* pictureStructure */
- ib_cpu[len + 62] = 0; /* encPicType -ref[1] */
- ib_cpu[len + 67] = 0; /* pictureStructure */
- ib_cpu[len + 68] = 0; /* encPicType -ref1 */
- ib_cpu[len + 81] = 1; /* frameNumber */
- ib_cpu[len + 82] = 2; /* pictureOrderCount */
- ib_cpu[len + 83] = 0xffffffff; /* numIPicRemainInRCGOP */
- ib_cpu[len + 84] = 0xffffffff; /* numPPicRemainInRCGOP */
- ib_cpu[len + 85] = 0xffffffff; /* numBPicRemainInRCGOP */
- ib_cpu[len + 86] = 0xffffffff; /* numIRPicRemainInRCGOP */
- ib_cpu[len + 87] = 0; /* remainedIntraRefreshPictures */
- len += sizeof(vce_encode) / 4;
-
- enc->ib_len = len;
- r = submit(len, AMDGPU_HW_IP_VCE);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void check_mv_result(struct amdgpu_vce_encode *enc)
-{
- uint64_t sum;
- uint32_t s = 140790;
- int j, r;
-
- r = amdgpu_bo_cpu_map(enc->fb[0].handle, (void **)&enc->fb[0].ptr);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_cpu_unmap(enc->fb[0].handle);
- CU_ASSERT_EQUAL(r, 0);
- r = amdgpu_bo_cpu_map(enc->mvb.handle, (void **)&enc->mvb.ptr);
- CU_ASSERT_EQUAL(r, 0);
- for (j = 0, sum = 0; j < enc->mvbuf_size; ++j)
- sum += enc->mvb.ptr[j];
- CU_ASSERT_EQUAL(sum, s);
- r = amdgpu_bo_cpu_unmap(enc->mvb.handle);
- CU_ASSERT_EQUAL(r, 0);
-}
-
-static void amdgpu_cs_vce_encode_mv(void)
-{
- uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
- unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
- int i, r;
-
- vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
- enc.mvbuf_size = ALIGN(enc.width, 16) * ALIGN(enc.height, 16) / 8;
- cpb_size = vbuf_size * 10;
- num_resources = 0;
- alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT);
- resources[num_resources++] = enc.fb[0].handle;
- alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT);
- resources[num_resources++] = enc.bs[0].handle;
- alloc_resource(&enc.mvb, enc.mvbuf_size, AMDGPU_GEM_DOMAIN_GTT);
- resources[num_resources++] = enc.mvb.handle;
- alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
- resources[num_resources++] = enc.vbuf.handle;
- alloc_resource(&enc.mvrefbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
- resources[num_resources++] = enc.mvrefbuf.handle;
- alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
- resources[num_resources++] = enc.cpb.handle;
- resources[num_resources++] = ib_handle;
-
- r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
- CU_ASSERT_EQUAL(r, 0);
-
- memset(enc.vbuf.ptr, 0, vbuf_size);
- for (i = 0; i < enc.height; ++i) {
- memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
- enc.vbuf.ptr += ALIGN(enc.width, align);
- }
- for (i = 0; i < enc.height / 2; ++i) {
- memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width);
- enc.vbuf.ptr += ALIGN(enc.width, align);
- }
-
- r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_bo_cpu_map(enc.mvrefbuf.handle, (void **)&enc.mvrefbuf.ptr);
- CU_ASSERT_EQUAL(r, 0);
-
- memset(enc.mvrefbuf.ptr, 0, vbuf_size);
- for (i = 0; i < enc.height; ++i) {
- memcpy(enc.mvrefbuf.ptr, (frame + (enc.height - i -1) * enc.width), enc.width);
- enc.mvrefbuf.ptr += ALIGN(enc.width, align);
- }
- for (i = 0; i < enc.height / 2; ++i) {
- memcpy(enc.mvrefbuf.ptr,
- ((frame + enc.height * enc.width) + (enc.height / 2 - i -1) * enc.width), enc.width);
- enc.mvrefbuf.ptr += ALIGN(enc.width, align);
- }
-
- r = amdgpu_bo_cpu_unmap(enc.mvrefbuf.handle);
- CU_ASSERT_EQUAL(r, 0);
-
- amdgpu_cs_vce_config();
-
- vce_taskinfo[3] = 3;
- amdgpu_cs_vce_mv(&enc);
- check_mv_result(&enc);
-
- free_resource(&enc.fb[0]);
- free_resource(&enc.bs[0]);
- free_resource(&enc.vbuf);
- free_resource(&enc.cpb);
- free_resource(&enc.mvrefbuf);
- free_resource(&enc.mvb);
-}
-
static void amdgpu_cs_vce_destroy(void)
{
int len, r;
diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index ad438f3..d9f05af 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -44,14 +44,6 @@
uint8_t *ptr;
};
-struct amdgpu_vcn_reg {
- uint32_t data0;
- uint32_t data1;
- uint32_t cmd;
- uint32_t nop;
- uint32_t cntl;
-};
-
static amdgpu_device_handle device_handle;
static uint32_t major_version;
static uint32_t minor_version;
@@ -65,7 +57,6 @@
static amdgpu_bo_handle resources[MAX_RESOURCES];
static unsigned num_resources;
-static struct amdgpu_vcn_reg reg;
static void amdgpu_cs_vcn_dec_create(void);
static void amdgpu_cs_vcn_dec_decode(void);
@@ -105,21 +96,6 @@
return CU_FALSE;
}
- if (family_id == AMDGPU_FAMILY_RV) {
- reg.data0 = 0x81c4;
- reg.data1 = 0x81c5;
- reg.cmd = 0x81c3;
- reg.nop = 0x81ff;
- reg.cntl = 0x81c6;
- } else if (family_id == AMDGPU_FAMILY_NV) {
- reg.data0 = 0x504;
- reg.data1 = 0x505;
- reg.cmd = 0x503;
- reg.nop = 0x53f;
- reg.cntl = 0x506;
- } else
- return CU_FALSE;
-
return CU_TRUE;
}
@@ -261,11 +237,11 @@
static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
{
- ib_cpu[(*idx)++] = reg.data0;
+ ib_cpu[(*idx)++] = 0x81C4;
ib_cpu[(*idx)++] = addr;
- ib_cpu[(*idx)++] = reg.data1;
+ ib_cpu[(*idx)++] = 0x81C5;
ib_cpu[(*idx)++] = addr >> 32;
- ib_cpu[(*idx)++] = reg.cmd;
+ ib_cpu[(*idx)++] = 0x81C3;
ib_cpu[(*idx)++] = cmd << 1;
}
@@ -286,16 +262,14 @@
memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
len = 0;
- ib_cpu[len++] = reg.data0;
+ ib_cpu[len++] = 0x81C4;
ib_cpu[len++] = msg_buf.addr;
- ib_cpu[len++] = reg.data1;
+ ib_cpu[len++] = 0x81C5;
ib_cpu[len++] = msg_buf.addr >> 32;
- ib_cpu[len++] = reg.cmd;
+ ib_cpu[len++] = 0x81C3;
ib_cpu[len++] = 0;
- for (; len % 16; ) {
- ib_cpu[len++] = reg.nop;
- ib_cpu[len++] = 0;
- }
+ for (; len % 16; ++len)
+ ib_cpu[len] = 0x81ff;
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
@@ -360,12 +334,10 @@
vcn_dec_cmd(it_addr, 0x204, &len);
vcn_dec_cmd(ctx_addr, 0x206, &len);
- ib_cpu[len++] = reg.cntl;
+ ib_cpu[len++] = 0x81C6;
ib_cpu[len++] = 0x1;
- for (; len % 16; ) {
- ib_cpu[len++] = reg.nop;
- ib_cpu[len++] = 0;
- }
+ for (; len % 16; ++len)
+ ib_cpu[len] = 0x80000000;
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
@@ -395,16 +367,14 @@
memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
len = 0;
- ib_cpu[len++] = reg.data0;
+ ib_cpu[len++] = 0x81C4;
ib_cpu[len++] = msg_buf.addr;
- ib_cpu[len++] = reg.data1;
+ ib_cpu[len++] = 0x81C5;
ib_cpu[len++] = msg_buf.addr >> 32;
- ib_cpu[len++] = reg.cmd;
+ ib_cpu[len++] = 0x81C3;
ib_cpu[len++] = 0;
- for (; len % 16; ) {
- ib_cpu[len++] = reg.nop;
- ib_cpu[len++] = 0;
- }
+ for (; len % 16; ++len)
+ ib_cpu[len] = 0x80000000;
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c
index 69bc468..7b6dc5d 100644
--- a/tests/amdgpu/vm_tests.c
+++ b/tests/amdgpu/vm_tests.c
@@ -31,9 +31,8 @@
static uint32_t major_version;
static uint32_t minor_version;
+
static void amdgpu_vmid_reserve_test(void);
-static void amdgpu_vm_unaligned_map(void);
-static void amdgpu_vm_mapping_test(void);
CU_BOOL suite_vm_tests_enable(void)
{
@@ -85,8 +84,6 @@
CU_TestInfo vm_tests[] = {
{ "resere vmid test", amdgpu_vmid_reserve_test },
- { "unaligned map", amdgpu_vm_unaligned_map },
- { "vm mapping test", amdgpu_vm_mapping_test },
CU_TEST_INFO_NULL,
};
@@ -170,86 +167,3 @@
r = amdgpu_cs_ctx_free(context_handle);
CU_ASSERT_EQUAL(r, 0);
}
-
-static void amdgpu_vm_unaligned_map(void)
-{
- const uint64_t map_size = (4ULL << 30) - (2 << 12);
- struct amdgpu_bo_alloc_request request = {};
- amdgpu_bo_handle buf_handle;
- amdgpu_va_handle handle;
- uint64_t vmc_addr;
- int r;
-
- request.alloc_size = 4ULL << 30;
- request.phys_alignment = 4096;
- request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
- request.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-
- r = amdgpu_bo_alloc(device_handle, &request, &buf_handle);
- /* Don't let the test fail if the device doesn't have enough VRAM */
- if (r)
- return;
-
- r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
- 4ULL << 30, 1ULL << 30, 0, &vmc_addr,
- &handle, 0);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- goto error_va_alloc;
-
- vmc_addr += 1 << 12;
-
- r = amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0,
- AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
- if (r)
- goto error_va_alloc;
-
- amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0,
- AMDGPU_VA_OP_UNMAP);
-
-error_va_alloc:
- amdgpu_bo_free(buf_handle);
-}
-
-static void amdgpu_vm_mapping_test(void)
-{
- struct amdgpu_bo_alloc_request req = {0};
- struct drm_amdgpu_info_device dev_info;
- const uint64_t size = 4096;
- amdgpu_bo_handle buf;
- uint64_t addr;
- int r;
-
- req.alloc_size = size;
- req.phys_alignment = 0;
- req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
- req.flags = 0;
-
- r = amdgpu_bo_alloc(device_handle, &req, &buf);
- CU_ASSERT_EQUAL(r, 0);
-
- r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO,
- sizeof(dev_info), &dev_info);
- CU_ASSERT_EQUAL(r, 0);
-
- addr = dev_info.virtual_address_offset;
- r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
-
- addr = dev_info.virtual_address_max - size;
- r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
-
- if (dev_info.high_va_offset) {
- addr = dev_info.high_va_offset;
- r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
-
- addr = dev_info.high_va_max - size;
- r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP);
- CU_ASSERT_EQUAL(r, 0);
- }
-
- amdgpu_bo_free(buf);
-}
diff --git a/tests/drmdevice.c b/tests/drmdevice.c
index f1c1cd3..9dd5098 100644
--- a/tests/drmdevice.c
+++ b/tests/drmdevice.c
@@ -36,66 +36,67 @@
print_device_info(drmDevicePtr device, int i, bool print_revision)
{
printf("device[%i]\n", i);
- printf("+-> available_nodes %#04x\n", device->available_nodes);
- printf("+-> nodes\n");
+ printf("\tavailable_nodes %04x\n", device->available_nodes);
+ printf("\tnodes\n");
for (int j = 0; j < DRM_NODE_MAX; j++)
if (device->available_nodes & 1 << j)
- printf("| +-> nodes[%d] %s\n", j, device->nodes[j]);
+ printf("\t\tnodes[%d] %s\n", j, device->nodes[j]);
- printf("+-> bustype %04x\n", device->bustype);
+ printf("\tbustype %04x\n", device->bustype);
+ printf("\tbusinfo\n");
if (device->bustype == DRM_BUS_PCI) {
- printf("| +-> pci\n");
- printf("| +-> domain %04x\n",device->businfo.pci->domain);
- printf("| +-> bus %02x\n", device->businfo.pci->bus);
- printf("| +-> dev %02x\n", device->businfo.pci->dev);
- printf("| +-> func %1u\n", device->businfo.pci->func);
+ printf("\t\tpci\n");
+ printf("\t\t\tdomain\t%04x\n",device->businfo.pci->domain);
+ printf("\t\t\tbus\t%02x\n", device->businfo.pci->bus);
+ printf("\t\t\tdev\t%02x\n", device->businfo.pci->dev);
+ printf("\t\t\tfunc\t%1u\n", device->businfo.pci->func);
- printf("+-> deviceinfo\n");
- printf(" +-> pci\n");
- printf(" +-> vendor_id %04x\n", device->deviceinfo.pci->vendor_id);
- printf(" +-> device_id %04x\n", device->deviceinfo.pci->device_id);
- printf(" +-> subvendor_id %04x\n", device->deviceinfo.pci->subvendor_id);
- printf(" +-> subdevice_id %04x\n", device->deviceinfo.pci->subdevice_id);
+ printf("\tdeviceinfo\n");
+ printf("\t\tpci\n");
+ printf("\t\t\tvendor_id\t%04x\n", device->deviceinfo.pci->vendor_id);
+ printf("\t\t\tdevice_id\t%04x\n", device->deviceinfo.pci->device_id);
+ printf("\t\t\tsubvendor_id\t%04x\n", device->deviceinfo.pci->subvendor_id);
+ printf("\t\t\tsubdevice_id\t%04x\n", device->deviceinfo.pci->subdevice_id);
if (print_revision)
- printf(" +-> revision_id %02x\n", device->deviceinfo.pci->revision_id);
+ printf("\t\t\trevision_id\t%02x\n", device->deviceinfo.pci->revision_id);
else
- printf(" +-> revision_id IGNORED\n");
+ printf("\t\t\trevision_id\tIGNORED\n");
} else if (device->bustype == DRM_BUS_USB) {
- printf("| +-> usb\n");
- printf("| +-> bus %03u\n", device->businfo.usb->bus);
- printf("| +-> dev %03u\n", device->businfo.usb->dev);
+ printf("\t\tusb\n");
+ printf("\t\t\tbus\t%03u\n", device->businfo.usb->bus);
+ printf("\t\t\tdev\t%03u\n", device->businfo.usb->dev);
- printf("+-> deviceinfo\n");
- printf(" +-> usb\n");
- printf(" +-> vendor %04x\n", device->deviceinfo.usb->vendor);
- printf(" +-> product %04x\n", device->deviceinfo.usb->product);
+ printf("\tdeviceinfo\n");
+ printf("\t\tusb\n");
+ printf("\t\t\tvendor\t%04x\n", device->deviceinfo.usb->vendor);
+ printf("\t\t\tproduct\t%04x\n", device->deviceinfo.usb->product);
} else if (device->bustype == DRM_BUS_PLATFORM) {
char **compatible = device->deviceinfo.platform->compatible;
- printf("| +-> platform\n");
- printf("| +-> fullname\t%s\n", device->businfo.platform->fullname);
+ printf("\t\tplatform\n");
+ printf("\t\t\tfullname\t%s\n", device->businfo.platform->fullname);
- printf("+-> deviceinfo\n");
- printf(" +-> platform\n");
- printf(" +-> compatible\n");
+ printf("\tdeviceinfo\n");
+ printf("\t\tplatform\n");
+ printf("\t\t\tcompatible\n");
while (*compatible) {
- printf(" %s\n", *compatible);
+ printf("\t\t\t\t%s\n", *compatible);
compatible++;
}
} else if (device->bustype == DRM_BUS_HOST1X) {
- char **compatible = device->deviceinfo.host1x->compatible;
+ char **compatible = device->deviceinfo.platform->compatible;
- printf("| +-> host1x\n");
- printf("| +-> fullname\t%s\n", device->businfo.host1x->fullname);
+ printf("\t\thost1x\n");
+ printf("\t\t\tfullname\t%s\n", device->businfo.host1x->fullname);
- printf("+-> deviceinfo\n");
- printf(" +-> host1x\n");
- printf(" +-> compatible\n");
+ printf("\tdeviceinfo\n");
+ printf("\t\tplatform\n");
+ printf("\t\t\tcompatible\n");
while (*compatible) {
- printf(" %s\n", *compatible);
+ printf("\t\t\t\t%s\n", *compatible);
compatible++;
}
} else {
@@ -111,16 +112,12 @@
drmDevicePtr device;
int fd, ret, max_devices;
- printf("--- Checking the number of DRM device available ---\n");
max_devices = drmGetDevices2(0, NULL, 0);
if (max_devices <= 0) {
- printf("drmGetDevices2() has not found any devices (errno=%d)\n",
- -max_devices);
- return 77;
+ printf("drmGetDevices2() has returned %d\n", max_devices);
+ return -1;
}
- printf("--- Devices reported %d ---\n", max_devices);
-
devices = calloc(max_devices, sizeof(drmDevicePtr));
if (devices == NULL) {
@@ -128,7 +125,6 @@
return -1;
}
- printf("--- Retrieving devices information (PCI device revision is ignored) ---\n");
ret = drmGetDevices2(0, devices, max_devices);
if (ret < 0) {
printf("drmGetDevices2() returned an error %d\n", ret);
@@ -141,14 +137,13 @@
for (int j = 0; j < DRM_NODE_MAX; j++) {
if (devices[i]->available_nodes & 1 << j) {
- printf("--- Opening device node %s ---\n", devices[i]->nodes[j]);
+ printf("Opening device %d node %s\n", i, devices[i]->nodes[j]);
fd = open(devices[i]->nodes[j], O_RDONLY | O_CLOEXEC, 0);
if (fd < 0) {
printf("Failed - %s (%d)\n", strerror(errno), errno);
continue;
}
- printf("--- Retrieving device info, for node %s ---\n", devices[i]->nodes[j]);
if (drmGetDevice2(fd, DRM_DEVICE_GET_PCI_REVISION, &device) == 0) {
print_device_info(device, i, true);
drmFreeDevice(&device);
diff --git a/tests/etnaviv/Makefile.am b/tests/etnaviv/Makefile.am
index 3e0c612..226baee 100644
--- a/tests/etnaviv/Makefile.am
+++ b/tests/etnaviv/Makefile.am
@@ -1,5 +1,4 @@
AM_CFLAGS = \
- -fvisibility=hidden \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)/etnaviv \
-I $(top_srcdir)
diff --git a/tests/exynos/Makefile.am b/tests/exynos/Makefile.am
index 9658fb4..b636172 100644
--- a/tests/exynos/Makefile.am
+++ b/tests/exynos/Makefile.am
@@ -1,7 +1,6 @@
AM_CFLAGS = \
-pthread \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)/libkms/ \
-I $(top_srcdir)/exynos \
diff --git a/tests/exynos/meson.build b/tests/exynos/meson.build
index 3a048e8..940c3ce 100644
--- a/tests/exynos/meson.build
+++ b/tests/exynos/meson.build
@@ -24,7 +24,7 @@
exynos_fimg2d_test = executable(
'exynos_fimg2d_test',
files('exynos_fimg2d_test.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm, inc_exynos,
include_directories('../../libkms')],
link_with : [libdrm, libkms, libdrm_exynos],
@@ -36,7 +36,7 @@
exynos_fimg2d_perf = executable(
'exynos_fimg2d_perf',
files('exynos_fimg2d_perf.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm, inc_exynos],
link_with : [libdrm, libdrm_exynos],
dependencies : dep_threads,
@@ -46,7 +46,7 @@
exynos_fimg2d_event = executable(
'exynos_fimg2d_event',
files('exynos_fimg2d_event.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_drm, inc_exynos],
link_with : [libdrm, libdrm_exynos],
dependencies : dep_threads,
diff --git a/tests/kms/Makefile.am b/tests/kms/Makefile.am
index 4224200..6645af7 100644
--- a/tests/kms/Makefile.am
+++ b/tests/kms/Makefile.am
@@ -4,8 +4,7 @@
-I$(top_srcdir)
AM_CFLAGS = \
- $(WARN_CFLAGS) \
- -fvisibility=hidden
+ $(WARN_CFLAGS)
noinst_LTLIBRARIES = libkms-test.la
diff --git a/tests/kms/libkms-test-plane.c b/tests/kms/libkms-test-plane.c
index 4cb2737..6c40a3c 100644
--- a/tests/kms/libkms-test-plane.c
+++ b/tests/kms/libkms-test-plane.c
@@ -55,10 +55,8 @@
}
plane->formats = calloc(p->count_formats, sizeof(uint32_t));
- if (!plane->formats) {
- drmModeFreePlane(p);
+ if (!plane->formats)
return -ENOMEM;
- }
for (i = 0; i < p->count_formats; i++)
plane->formats[i] = p->formats[i];
diff --git a/tests/kms/meson.build b/tests/kms/meson.build
index 91371aa..1f7f724 100644
--- a/tests/kms/meson.build
+++ b/tests/kms/meson.build
@@ -27,7 +27,7 @@
),
include_directories : [inc_root, inc_tests, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
kms_steal_crtc = executable(
diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am
index 4c993b0..ced541b 100644
--- a/tests/kmstest/Makefile.am
+++ b/tests/kmstest/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/libkms/ \
-I$(top_srcdir)/tests/ \
diff --git a/tests/kmstest/meson.build b/tests/kmstest/meson.build
index 4fb870f..a47d495 100644
--- a/tests/kmstest/meson.build
+++ b/tests/kmstest/meson.build
@@ -21,7 +21,7 @@
kmstest = executable(
'kmstest',
files('main.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [
inc_root, inc_tests, include_directories('../../libkms'), inc_drm,
],
diff --git a/tests/meson.build b/tests/meson.build
index 6c8ddd9..fdf950b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -53,7 +53,7 @@
files('drmsl.c'),
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
hash = executable(
@@ -61,7 +61,7 @@
files('hash.c'),
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
random = executable(
@@ -69,7 +69,7 @@
files('random.c'),
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
drmdevice = executable(
@@ -77,7 +77,7 @@
files('drmdevice.c'),
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
test('random', random, timeout : 240)
diff --git a/tests/modeprint/Makefile.am b/tests/modeprint/Makefile.am
index 568185f..601dbc9 100644
--- a/tests/modeprint/Makefile.am
+++ b/tests/modeprint/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/tests \
-I$(top_srcdir)
@@ -16,5 +15,4 @@
modeprint_SOURCES = \
modeprint.c
modeprint_LDADD = \
- $(top_builddir)/tests/util/libutil.la \
$(top_builddir)/libdrm.la
diff --git a/tests/modeprint/meson.build b/tests/modeprint/meson.build
index 0801808..5f0eb24 100644
--- a/tests/modeprint/meson.build
+++ b/tests/modeprint/meson.build
@@ -21,9 +21,9 @@
modeprint = executable(
'modeprint',
files('modeprint.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_tests, inc_drm],
- link_with : [libdrm, libutil],
+ link_with : libdrm,
dependencies : dep_threads,
install : with_install_tests,
)
diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c
index ad727e1..c81dd91 100644
--- a/tests/modeprint/modeprint.c
+++ b/tests/modeprint/modeprint.c
@@ -42,7 +42,6 @@
#include "xf86drmMode.h"
#include "util/common.h"
-#include "util/kms.h"
int current;
int connectors;
@@ -55,6 +54,20 @@
int fbs;
char *module_name;
+static const char* getConnectionText(drmModeConnection conn)
+{
+ switch (conn) {
+ case DRM_MODE_CONNECTED:
+ return "connected";
+ case DRM_MODE_DISCONNECTED:
+ return "disconnected";
+ case DRM_MODE_UNKNOWNCONNECTION:
+ default:
+ return "unknown";
+ }
+
+}
+
static int printMode(struct drm_mode_modeinfo *mode)
{
if (full_modes) {
@@ -128,24 +141,40 @@
return 0;
}
+static const char * const output_names[] = { "None",
+ "VGA",
+ "DVI-I",
+ "DVI-D",
+ "DVI-A",
+ "Composite",
+ "SVIDEO",
+ "LVDS",
+ "Component",
+ "DIN",
+ "DP",
+ "HDMI-A",
+ "HDMI-B",
+ "TV",
+ "eDP",
+ "Virtual",
+ "DSI",
+};
+
static int printConnector(int fd, drmModeResPtr res, drmModeConnectorPtr connector, uint32_t id)
{
int i = 0;
struct drm_mode_modeinfo *mode = NULL;
drmModePropertyPtr props;
- const char *connector_type_name = NULL;
- connector_type_name = util_lookup_connector_type_name(connector->connector_type);
-
- if (connector_type_name)
- printf("Connector: %s-%d\n", connector_type_name,
+ if (connector->connector_type < ARRAY_SIZE(output_names))
+ printf("Connector: %s-%d\n", output_names[connector->connector_type],
connector->connector_type_id);
else
printf("Connector: %d-%d\n", connector->connector_type,
connector->connector_type_id);
printf("\tid : %i\n", id);
printf("\tencoder id : %i\n", connector->encoder_id);
- printf("\tconn : %s\n", util_lookup_connector_status_name(connector->connection));
+ printf("\tconn : %s\n", getConnectionText(connector->connection));
printf("\tsize : %ix%i (mm)\n", connector->mmWidth, connector->mmHeight);
printf("\tcount_modes : %i\n", connector->count_modes);
printf("\tcount_props : %i\n", connector->count_props);
@@ -186,13 +215,7 @@
static int printEncoder(int fd, drmModeResPtr res, drmModeEncoderPtr encoder, uint32_t id)
{
- const char *encoder_name;
-
- encoder_name = util_lookup_encoder_type_name(encoder->encoder_type);
- if (encoder_name)
- printf("Encoder: %s\n", encoder_name);
- else
- printf("Encoder\n");
+ printf("Encoder\n");
printf("\tid :%i\n", id);
printf("\tcrtc_id :%d\n", encoder->crtc_id);
printf("\ttype :%d\n", encoder->encoder_type);
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index 5eebd96..4b296c8 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -3,7 +3,6 @@
AM_CFLAGS = $(filter-out -Wpointer-arith, $(WARN_CFLAGS))
AM_CFLAGS += \
- -fvisibility=hidden \
-pthread \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/tests \
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
index 8a8d9e0..9b635c0 100644
--- a/tests/modetest/buffers.c
+++ b/tests/modetest/buffers.c
@@ -135,7 +135,6 @@
int ret;
switch (format) {
- case DRM_FORMAT_C8:
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
@@ -194,13 +193,6 @@
bpp = 32;
break;
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
- bpp = 64;
- break;
-
default:
fprintf(stderr, "unsupported format 0x%08x\n", format);
return NULL;
@@ -283,7 +275,6 @@
planes[2] = virtual + offsets[2];
break;
- case DRM_FORMAT_C8:
case DRM_FORMAT_ARGB4444:
case DRM_FORMAT_XRGB4444:
case DRM_FORMAT_ABGR4444:
@@ -320,10 +311,6 @@
case DRM_FORMAT_RGBX1010102:
case DRM_FORMAT_BGRA1010102:
case DRM_FORMAT_BGRX1010102:
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
offsets[0] = 0;
handles[0] = bo->handle;
pitches[0] = bo->pitch;
diff --git a/tests/modetest/meson.build b/tests/modetest/meson.build
index 23d84a1..2a08184 100644
--- a/tests/modetest/meson.build
+++ b/tests/modetest/meson.build
@@ -21,7 +21,7 @@
modetest = executable(
'modetest',
files('buffers.c', 'cursor.c', 'modetest.c'),
- c_args : [libdrm_c_args, '-Wno-pointer-arith'],
+ c_args : [warn_c_args, '-Wno-pointer-arith'],
include_directories : [inc_root, inc_tests, inc_drm],
dependencies : [dep_threads, dep_cairo],
link_with : [libdrm, libutil],
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index e66be66..62957d8 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -67,9 +67,6 @@
#include "buffers.h"
#include "cursor.h"
-static enum util_fill_pattern primary_fill = UTIL_PATTERN_SMPTE;
-static enum util_fill_pattern secondary_fill = UTIL_PATTERN_TILES;
-
struct crtc {
drmModeCrtc *crtc;
drmModeObjectProperties *props;
@@ -122,9 +119,6 @@
struct bo *bo;
struct bo *cursor_bo;
} mode;
-
- int use_atomic;
- drmModeAtomicReq *req;
};
static inline int64_t U642I64(uint64_t val)
@@ -296,8 +290,6 @@
return "NVIDIA_16BX2_BLOCK(5)";
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
return "MOD_BROADCOM_VC4_T_TILED";
- case DRM_FORMAT_MOD_QCOM_COMPRESSED:
- return "QCOM_COMPRESSED";
default:
return "(UNKNOWN MODIFIER)";
}
@@ -813,9 +805,7 @@
uint32_t w, h;
double scale;
unsigned int fb_id;
- unsigned int old_fb_id;
struct bo *bo;
- struct bo *old_bo;
char format_str[5]; /* need to leave room for terminating \0 */
unsigned int fourcc;
};
@@ -951,10 +941,9 @@
char name[DRM_PROP_NAME_LEN+1];
uint32_t prop_id;
uint64_t value;
- bool optional;
};
-static bool set_property(struct device *dev, struct property_arg *p)
+static void set_property(struct device *dev, struct property_arg *p)
{
drmModeObjectProperties *props = NULL;
drmModePropertyRes **props_info = NULL;
@@ -986,13 +975,13 @@
if (p->obj_type == 0) {
fprintf(stderr, "Object %i not found, can't set property\n",
p->obj_id);
- return false;
+ return;
}
if (!props) {
fprintf(stderr, "%s %i has no properties\n",
obj_type, p->obj_id);
- return false;
+ return;
}
for (i = 0; i < (int)props->count_props; ++i) {
@@ -1003,25 +992,18 @@
}
if (i == (int)props->count_props) {
- if (!p->optional)
- fprintf(stderr, "%s %i has no %s property\n",
- obj_type, p->obj_id, p->name);
- return false;
+ fprintf(stderr, "%s %i has no %s property\n",
+ obj_type, p->obj_id, p->name);
+ return;
}
p->prop_id = props->props[i];
- if (!dev->use_atomic)
- ret = drmModeObjectSetProperty(dev->fd, p->obj_id, p->obj_type,
- p->prop_id, p->value);
- else
- ret = drmModeAtomicAddProperty(dev->req, p->obj_id, p->prop_id, p->value);
-
+ ret = drmModeObjectSetProperty(dev->fd, p->obj_id, p->obj_type,
+ p->prop_id, p->value);
if (ret < 0)
fprintf(stderr, "failed to set %s %i property %s to %" PRIu64 ": %s\n",
obj_type, p->obj_id, p->name, p->value, strerror(errno));
-
- return true;
}
/* -------------------------------------------------------------------------- */
@@ -1067,143 +1049,6 @@
return false;
}
-static void add_property(struct device *dev, uint32_t obj_id,
- const char *name, uint64_t value)
-{
- struct property_arg p;
-
- p.obj_id = obj_id;
- strcpy(p.name, name);
- p.value = value;
-
- set_property(dev, &p);
-}
-
-static bool add_property_optional(struct device *dev, uint32_t obj_id,
- const char *name, uint64_t value)
-{
- struct property_arg p;
-
- p.obj_id = obj_id;
- strcpy(p.name, name);
- p.value = value;
- p.optional = true;
-
- return set_property(dev, &p);
-}
-
-static void set_gamma(struct device *dev, unsigned crtc_id, unsigned fourcc)
-{
- unsigned blob_id = 0;
- /* TODO: support 1024-sized LUTs, when the use-case arises */
- struct drm_color_lut gamma_lut[256];
- int i, ret;
-
- if (fourcc == DRM_FORMAT_C8) {
- /* TODO: Add C8 support for more patterns */
- util_smpte_c8_gamma(256, gamma_lut);
- drmModeCreatePropertyBlob(dev->fd, gamma_lut, sizeof(gamma_lut), &blob_id);
- } else {
- for (i = 0; i < 256; i++) {
- gamma_lut[i].red =
- gamma_lut[i].green =
- gamma_lut[i].blue = i << 8;
- }
- }
-
- add_property_optional(dev, crtc_id, "DEGAMMA_LUT", 0);
- add_property_optional(dev, crtc_id, "CTM", 0);
- if (!add_property_optional(dev, crtc_id, "GAMMA_LUT", blob_id)) {
- uint16_t r[256], g[256], b[256];
-
- for (i = 0; i < 256; i++) {
- r[i] = gamma_lut[i].red;
- g[i] = gamma_lut[i].green;
- b[i] = gamma_lut[i].blue;
- }
-
- ret = drmModeCrtcSetGamma(dev->fd, crtc_id, 256, r, g, b);
- if (ret)
- fprintf(stderr, "failed to set gamma: %s\n", strerror(errno));
- }
-}
-
-static int atomic_set_plane(struct device *dev, struct plane_arg *p,
- int pattern, bool update)
-{
- uint32_t handles[4] = {0}, pitches[4] = {0}, offsets[4] = {0};
- struct bo *plane_bo;
- int crtc_x, crtc_y, crtc_w, crtc_h;
- struct crtc *crtc = NULL;
- unsigned int i;
- unsigned int old_fb_id;
-
- /* Find an unused plane which can be connected to our CRTC. Find the
- * CRTC index first, then iterate over available planes.
- */
- for (i = 0; i < (unsigned int)dev->resources->res->count_crtcs; i++) {
- if (p->crtc_id == dev->resources->res->crtcs[i]) {
- crtc = &dev->resources->crtcs[i];
- break;
- }
- }
-
- if (!crtc) {
- fprintf(stderr, "CRTC %u not found\n", p->crtc_id);
- return -1;
- }
-
- if (!update)
- fprintf(stderr, "testing %dx%d@%s on plane %u, crtc %u\n",
- p->w, p->h, p->format_str, p->plane_id, p->crtc_id);
-
- plane_bo = p->old_bo;
- p->old_bo = p->bo;
-
- if (!plane_bo) {
- plane_bo = bo_create(dev->fd, p->fourcc, p->w, p->h,
- handles, pitches, offsets, pattern);
-
- if (plane_bo == NULL)
- return -1;
-
- if (drmModeAddFB2(dev->fd, p->w, p->h, p->fourcc,
- handles, pitches, offsets, &p->fb_id, 0)) {
- fprintf(stderr, "failed to add fb: %s\n", strerror(errno));
- return -1;
- }
- }
-
- p->bo = plane_bo;
-
- old_fb_id = p->fb_id;
- p->old_fb_id = old_fb_id;
-
- crtc_w = p->w * p->scale;
- crtc_h = p->h * p->scale;
- if (!p->has_position) {
- /* Default to the middle of the screen */
- crtc_x = (crtc->mode->hdisplay - crtc_w) / 2;
- crtc_y = (crtc->mode->vdisplay - crtc_h) / 2;
- } else {
- crtc_x = p->x;
- crtc_y = p->y;
- }
-
- add_property(dev, p->plane_id, "FB_ID", p->fb_id);
- add_property(dev, p->plane_id, "CRTC_ID", p->crtc_id);
- add_property(dev, p->plane_id, "SRC_X", 0);
- add_property(dev, p->plane_id, "SRC_Y", 0);
- add_property(dev, p->plane_id, "SRC_W", p->w << 16);
- add_property(dev, p->plane_id, "SRC_H", p->h << 16);
- add_property(dev, p->plane_id, "CRTC_X", crtc_x);
- add_property(dev, p->plane_id, "CRTC_Y", crtc_y);
- add_property(dev, p->plane_id, "CRTC_W", crtc_w);
- add_property(dev, p->plane_id, "CRTC_H", crtc_h);
-
- return 0;
-}
-
static int set_plane(struct device *dev, struct plane_arg *p)
{
drmModePlane *ovr;
@@ -1262,7 +1107,7 @@
p->w, p->h, p->format_str, plane_id);
plane_bo = bo_create(dev->fd, p->fourcc, p->w, p->h, handles,
- pitches, offsets, secondary_fill);
+ pitches, offsets, UTIL_PATTERN_TILES);
if (plane_bo == NULL)
return -1;
@@ -1300,66 +1145,6 @@
return 0;
}
-static void atomic_set_planes(struct device *dev, struct plane_arg *p,
- unsigned int count, bool update)
-{
- unsigned int i, pattern = primary_fill;
-
- /* set up planes */
- for (i = 0; i < count; i++) {
- if (i > 0)
- pattern = secondary_fill;
- else
- set_gamma(dev, p[i].crtc_id, p[i].fourcc);
-
- if (atomic_set_plane(dev, &p[i], pattern, update))
- return;
- }
-}
-
-static void atomic_clear_planes(struct device *dev, struct plane_arg *p, unsigned int count)
-{
- unsigned int i;
-
- for (i = 0; i < count; i++) {
- add_property(dev, p[i].plane_id, "FB_ID", 0);
- add_property(dev, p[i].plane_id, "CRTC_ID", 0);
- add_property(dev, p[i].plane_id, "SRC_X", 0);
- add_property(dev, p[i].plane_id, "SRC_Y", 0);
- add_property(dev, p[i].plane_id, "SRC_W", 0);
- add_property(dev, p[i].plane_id, "SRC_H", 0);
- add_property(dev, p[i].plane_id, "CRTC_X", 0);
- add_property(dev, p[i].plane_id, "CRTC_Y", 0);
- add_property(dev, p[i].plane_id, "CRTC_W", 0);
- add_property(dev, p[i].plane_id, "CRTC_H", 0);
- }
-}
-
-static void atomic_clear_FB(struct device *dev, struct plane_arg *p, unsigned int count)
-{
- unsigned int i;
-
- for (i = 0; i < count; i++) {
- if (p[i].fb_id) {
- drmModeRmFB(dev->fd, p[i].fb_id);
- p[i].fb_id = 0;
- }
- if (p[i].old_fb_id) {
- drmModeRmFB(dev->fd, p[i].old_fb_id);
- p[i].old_fb_id = 0;
- }
- if (p[i].bo) {
- bo_destroy(p[i].bo);
- p[i].bo = NULL;
- }
- if (p[i].old_bo) {
- bo_destroy(p[i].old_bo);
- p[i].old_bo = NULL;
- }
-
- }
-}
-
static void clear_planes(struct device *dev, struct plane_arg *p, unsigned int count)
{
unsigned int i;
@@ -1372,59 +1157,6 @@
}
}
-static void atomic_set_mode(struct device *dev, struct pipe_arg *pipes, unsigned int count)
-{
- unsigned int i;
- unsigned int j;
- int ret;
-
- for (i = 0; i < count; i++) {
- struct pipe_arg *pipe = &pipes[i];
-
- ret = pipe_find_crtc_and_mode(dev, pipe);
- if (ret < 0)
- continue;
- }
-
- for (i = 0; i < count; i++) {
- struct pipe_arg *pipe = &pipes[i];
- uint32_t blob_id;
-
- if (pipe->mode == NULL)
- continue;
-
- printf("setting mode %s-%dHz on connectors ",
- pipe->mode_str, pipe->mode->vrefresh);
- for (j = 0; j < pipe->num_cons; ++j) {
- printf("%s, ", pipe->cons[j]);
- add_property(dev, pipe->con_ids[j], "CRTC_ID", pipe->crtc->crtc->crtc_id);
- }
- printf("crtc %d\n", pipe->crtc->crtc->crtc_id);
-
- drmModeCreatePropertyBlob(dev->fd, pipe->mode, sizeof(*pipe->mode), &blob_id);
- add_property(dev, pipe->crtc->crtc->crtc_id, "MODE_ID", blob_id);
- add_property(dev, pipe->crtc->crtc->crtc_id, "ACTIVE", 1);
- }
-}
-
-static void atomic_clear_mode(struct device *dev, struct pipe_arg *pipes, unsigned int count)
-{
- unsigned int i;
- unsigned int j;
-
- for (i = 0; i < count; i++) {
- struct pipe_arg *pipe = &pipes[i];
-
- if (pipe->mode == NULL)
- continue;
-
- for (j = 0; j < pipe->num_cons; ++j)
- add_property(dev, pipe->con_ids[j], "CRTC_ID",0);
-
- add_property(dev, pipe->crtc->crtc->crtc_id, "MODE_ID", 0);
- add_property(dev, pipe->crtc->crtc->crtc_id, "ACTIVE", 0);
- }
-}
static void set_mode(struct device *dev, struct pipe_arg *pipes, unsigned int count)
{
@@ -1453,7 +1185,7 @@
bo = bo_create(dev->fd, pipes[0].fourcc, dev->mode.width,
dev->mode.height, handles, pitches, offsets,
- primary_fill);
+ UTIL_PATTERN_SMPTE);
if (bo == NULL)
return;
@@ -1495,8 +1227,6 @@
fprintf(stderr, "failed to set mode: %s\n", strerror(errno));
return;
}
-
- set_gamma(dev, pipe->crtc->crtc->crtc_id, pipe->fourcc);
}
}
@@ -1771,8 +1501,11 @@
}
if (*end == '@') {
- strncpy(plane->format_str, end + 1, 4);
- plane->format_str[4] = '\0';
+ p = end + 1;
+ if (strlen(p) != 4)
+ return -EINVAL;
+
+ strcpy(plane->format_str, p);
} else {
strcpy(plane->format_str, "XR24");
}
@@ -1797,21 +1530,9 @@
return 0;
}
-static void parse_fill_patterns(char *arg)
-{
- char *fill = strtok(arg, ",");
- if (!fill)
- return;
- primary_fill = util_pattern_enum(fill);
- fill = strtok(NULL, ",");
- if (!fill)
- return;
- secondary_fill = util_pattern_enum(fill);
-}
-
static void usage(char *name)
{
- fprintf(stderr, "usage: %s [-acDdefMPpsCvw]\n", name);
+ fprintf(stderr, "usage: %s [-cDdefMPpsCvw]\n", name);
fprintf(stderr, "\n Query options:\n\n");
fprintf(stderr, "\t-c\tlist connectors\n");
@@ -1825,8 +1546,6 @@
fprintf(stderr, "\t-C\ttest hw cursor\n");
fprintf(stderr, "\t-v\ttest vsynced page flipping\n");
fprintf(stderr, "\t-w <obj_id>:<prop_name>:<value>\tset property\n");
- fprintf(stderr, "\t-a \tuse atomic API\n");
- fprintf(stderr, "\t-F pattern1,pattern2\tspecify fill patterns\n");
fprintf(stderr, "\n Generic options:\n\n");
fprintf(stderr, "\t-d\tdrop master after mode set\n");
@@ -1890,7 +1609,7 @@
return 0;
}
-static char optstr[] = "acdD:efF:M:P:ps:Cvw:";
+static char optstr[] = "cdD:efM:P:ps:Cvw:";
int main(int argc, char **argv)
{
@@ -1901,7 +1620,6 @@
int drop_master = 0;
int test_vsync = 0;
int test_cursor = 0;
- int use_atomic = 0;
char *device = NULL;
char *module = NULL;
unsigned int i;
@@ -1920,9 +1638,6 @@
args++;
switch (c) {
- case 'a':
- use_atomic = 1;
- break;
case 'c':
connectors = 1;
break;
@@ -1939,9 +1654,6 @@
case 'f':
framebuffers = 1;
break;
- case 'F':
- parse_fill_patterns(optarg);
- break;
case 'M':
module = optarg;
/* Preserve the default behaviour of dumping all information. */
@@ -2005,22 +1717,13 @@
}
}
- if (!args || (args == 1 && use_atomic))
+ if (!args)
encoders = connectors = crtcs = planes = framebuffers = 1;
dev.fd = util_open(device, module);
if (dev.fd < 0)
return -1;
- ret = drmSetClientCap(dev.fd, DRM_CLIENT_CAP_ATOMIC, 1);
- if (ret && use_atomic) {
- fprintf(stderr, "no atomic modesetting support: %s\n", strerror(errno));
- drmClose(dev.fd);
- return -1;
- }
-
- dev.use_atomic = use_atomic;
-
if (test_vsync && !page_flipping_supported()) {
fprintf(stderr, "page flipping not supported by drm.\n");
return -1;
@@ -2061,111 +1764,40 @@
for (i = 0; i < prop_count; ++i)
set_property(&dev, &prop_args[i]);
- if (dev.use_atomic) {
- dev.req = drmModeAtomicAlloc();
+ if (count || plane_count) {
+ uint64_t cap = 0;
- if (count && plane_count) {
- uint64_t cap = 0;
-
- ret = drmGetCap(dev.fd, DRM_CAP_DUMB_BUFFER, &cap);
- if (ret || cap == 0) {
- fprintf(stderr, "driver doesn't support the dumb buffer API\n");
- return 1;
- }
-
- atomic_set_mode(&dev, pipe_args, count);
- atomic_set_planes(&dev, plane_args, plane_count, false);
-
- ret = drmModeAtomicCommit(dev.fd, dev.req, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
- if (ret) {
- fprintf(stderr, "Atomic Commit failed [1]\n");
- return 1;
- }
-
- gettimeofday(&pipe_args->start, NULL);
- pipe_args->swap_count = 0;
-
- while (test_vsync) {
- drmModeAtomicFree(dev.req);
- dev.req = drmModeAtomicAlloc();
- atomic_set_planes(&dev, plane_args, plane_count, true);
-
- ret = drmModeAtomicCommit(dev.fd, dev.req, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
- if (ret) {
- fprintf(stderr, "Atomic Commit failed [2]\n");
- return 1;
- }
-
- pipe_args->swap_count++;
- if (pipe_args->swap_count == 60) {
- struct timeval end;
- double t;
-
- gettimeofday(&end, NULL);
- t = end.tv_sec + end.tv_usec * 1e-6 -
- (pipe_args->start.tv_sec + pipe_args->start.tv_usec * 1e-6);
- fprintf(stderr, "freq: %.02fHz\n", pipe_args->swap_count / t);
- pipe_args->swap_count = 0;
- pipe_args->start = end;
- }
- }
-
- if (drop_master)
- drmDropMaster(dev.fd);
-
- getchar();
-
- drmModeAtomicFree(dev.req);
- dev.req = drmModeAtomicAlloc();
-
- atomic_clear_mode(&dev, pipe_args, count);
- atomic_clear_planes(&dev, plane_args, plane_count);
- ret = drmModeAtomicCommit(dev.fd, dev.req, DRM_MODE_ATOMIC_ALLOW_MODESET, NULL);
- if (ret) {
- fprintf(stderr, "Atomic Commit failed\n");
- return 1;
- }
-
- atomic_clear_FB(&dev, plane_args, plane_count);
+ ret = drmGetCap(dev.fd, DRM_CAP_DUMB_BUFFER, &cap);
+ if (ret || cap == 0) {
+ fprintf(stderr, "driver doesn't support the dumb buffer API\n");
+ return 1;
}
- drmModeAtomicFree(dev.req);
- } else {
- if (count || plane_count) {
- uint64_t cap = 0;
+ if (count)
+ set_mode(&dev, pipe_args, count);
- ret = drmGetCap(dev.fd, DRM_CAP_DUMB_BUFFER, &cap);
- if (ret || cap == 0) {
- fprintf(stderr, "driver doesn't support the dumb buffer API\n");
- return 1;
- }
+ if (plane_count)
+ set_planes(&dev, plane_args, plane_count);
- if (count)
- set_mode(&dev, pipe_args, count);
+ if (test_cursor)
+ set_cursors(&dev, pipe_args, count);
- if (plane_count)
- set_planes(&dev, plane_args, plane_count);
+ if (test_vsync)
+ test_page_flip(&dev, pipe_args, count);
- if (test_cursor)
- set_cursors(&dev, pipe_args, count);
+ if (drop_master)
+ drmDropMaster(dev.fd);
- if (test_vsync)
- test_page_flip(&dev, pipe_args, count);
+ getchar();
- if (drop_master)
- drmDropMaster(dev.fd);
+ if (test_cursor)
+ clear_cursors(&dev);
- getchar();
+ if (plane_count)
+ clear_planes(&dev, plane_args, plane_count);
- if (test_cursor)
- clear_cursors(&dev);
-
- if (plane_count)
- clear_planes(&dev, plane_args, plane_count);
-
- if (count)
- clear_mode(&dev);
- }
+ if (count)
+ clear_mode(&dev);
}
free_resources(dev.resources);
diff --git a/tests/nouveau/Makefile.am b/tests/nouveau/Makefile.am
index 554f43e..3c799a8 100644
--- a/tests/nouveau/Makefile.am
+++ b/tests/nouveau/Makefile.am
@@ -1,7 +1,6 @@
AM_CFLAGS = \
-pthread \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/nouveau \
-I$(top_srcdir)
diff --git a/tests/nouveau/meson.build b/tests/nouveau/meson.build
index ca4d44f..f5d73c1 100644
--- a/tests/nouveau/meson.build
+++ b/tests/nouveau/meson.build
@@ -24,7 +24,7 @@
dependencies : [dep_dl, dep_threads],
include_directories : [inc_root, inc_drm, include_directories('../../nouveau')],
link_with : [libdrm, libdrm_nouveau],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
test('threaded', threaded)
diff --git a/tests/planetest/Android.bp b/tests/planetest/Android.bp
new file mode 100644
index 0000000..16dfc5b
--- /dev/null
+++ b/tests/planetest/Android.bp
@@ -0,0 +1,33 @@
+build = ["Android.sources.bp"]
+
+cc_test {
+ name: "planetest",
+ defaults: [
+ "planetest_common_sources",
+ "planetest_sources",
+ ],
+ shared_libs: ["libdrm"],
+
+ cflags: [
+ "-Wall",
+ "-Werror",
+ "-Wno-unused-parameter",
+ "-Wno-pointer-arith",
+ ],
+}
+
+cc_test {
+ name: "atomictest",
+ defaults: [
+ "planetest_common_sources",
+ "atomictest_sources",
+ ],
+ shared_libs: ["libdrm"],
+
+ cflags: [
+ "-Wall",
+ "-Werror",
+ "-Wno-unused-parameter",
+ "-Wno-pointer-arith",
+ ],
+}
diff --git a/tests/planetest/Android.sources.bp b/tests/planetest/Android.sources.bp
new file mode 100644
index 0000000..4a35bb5
--- /dev/null
+++ b/tests/planetest/Android.sources.bp
@@ -0,0 +1,24 @@
+// Autogenerated with Android.sources.bp.mk
+
+cc_defaults {
+ name: "planetest_common_sources",
+ srcs: [
+ "bo.c",
+ "dev.c",
+ "modeset.c",
+ ],
+}
+
+cc_defaults {
+ name: "planetest_sources",
+ srcs: [
+ "planetest.c",
+ ],
+}
+
+cc_defaults {
+ name: "atomictest_sources",
+ srcs: [
+ "atomictest.c",
+ ],
+}
diff --git a/tests/planetest/Makefile.am b/tests/planetest/Makefile.am
new file mode 100644
index 0000000..b82d05b
--- /dev/null
+++ b/tests/planetest/Makefile.am
@@ -0,0 +1,30 @@
+include Makefile.sources
+
+AM_CFLAGS = $(filter-out -Wpointer-arith, $(WARN_CFLAGS))
+
+AM_CFLAGS += \
+ -I$(top_srcdir)/include/drm \
+ -I$(top_srcdir)/libkms/ \
+ -I$(top_srcdir)
+
+PLANETEST_COMMON_LDADD = \
+ $(top_builddir)/libdrm.la \
+ $(top_builddir)/libkms/libkms.la \
+ -lpthread
+
+if HAVE_INSTALL_TESTS
+bin_PROGRAMS = \
+ atomictest \
+ planetest
+else
+noinst_PROGRAMS = \
+ atomictest \
+ planetest
+endif
+
+atomictest_CFLAGS=-DUSE_ATOMIC_API ${AM_CFLAGS}
+atomictest_SOURCES=${PLANETEST_COMMON_FILES} ${ATOMICTEST_FILES}
+planetest_SOURCES=${PLANETEST_COMMON_FILES} ${PLANETEST_FILES}
+
+atomictest_LDADD=${PLANETEST_COMMON_LDADD}
+planetest_LDADD=${PLANETEST_COMMON_LDADD}
diff --git a/tests/planetest/Makefile.sources b/tests/planetest/Makefile.sources
new file mode 100644
index 0000000..3cbeb2b
--- /dev/null
+++ b/tests/planetest/Makefile.sources
@@ -0,0 +1,13 @@
+PLANETEST_COMMON_FILES := \
+ bo.c \
+ bo.h \
+ dev.c \
+ dev.h \
+ modeset.c \
+ modeset.h
+
+ATOMICTEST_FILES := \
+ atomictest.c
+
+PLANETEST_FILES := \
+ planetest.c
diff --git a/tests/planetest/atomictest.c b/tests/planetest/atomictest.c
new file mode 100644
index 0000000..891d242
--- /dev/null
+++ b/tests/planetest/atomictest.c
@@ -0,0 +1,151 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/select.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+#include <signal.h>
+#include <time.h>
+#include <errno.h>
+
+#include <xf86drm.h>
+
+#include "dev.h"
+#include "bo.h"
+#include "modeset.h"
+
+static int terminate = 0;
+
+static void sigint_handler(int arg)
+{
+ terminate = 1;
+}
+
+static void
+page_flip_handler(int fd, unsigned int sequence, unsigned int tv_sec,
+ unsigned int tv_usec, void *user_data)
+{
+}
+
+static void incrementor(int *inc, int *val, int increment, int lower, int upper)
+{
+ if(*inc > 0)
+ *inc = *val + increment >= upper ? -1 : 1;
+ else
+ *inc = *val - increment <= lower ? 1 : -1;
+ *val += *inc * increment;
+}
+
+int main(int argc, char *argv[])
+{
+ int ret, i, j, num_test_planes;
+ int x_inc = 1, x = 0, y_inc = 1, y = 0;
+ uint32_t plane_w = 128, plane_h = 128;
+ struct sp_dev *dev;
+ struct sp_plane **plane = NULL;
+ struct sp_crtc *test_crtc;
+ fd_set fds;
+ drmModeAtomicReqPtr pset;
+ drmEventContext event_context = {
+ .version = DRM_EVENT_CONTEXT_VERSION,
+ .page_flip_handler = page_flip_handler,
+ };
+ int card = 0, crtc = 0;
+
+ signal(SIGINT, sigint_handler);
+
+ parse_arguments(argc, argv, &card, &crtc);
+
+ dev = create_sp_dev(card);
+ if (!dev) {
+ printf("Failed to create sp_dev\n");
+ return -1;
+ }
+
+ if (crtc >= dev->num_crtcs) {
+ printf("Invalid crtc %d (num=%d)\n", crtc, dev->num_crtcs);
+ return -1;
+ }
+
+ ret = initialize_screens(dev);
+ if (ret) {
+ printf("Failed to initialize screens\n");
+ goto out;
+ }
+ test_crtc = &dev->crtcs[crtc];
+
+ plane = calloc(dev->num_planes, sizeof(*plane));
+ if (!plane) {
+ printf("Failed to allocate plane array\n");
+ goto out;
+ }
+
+ /* Create our planes */
+ num_test_planes = test_crtc->num_planes;
+ for (i = 0; i < num_test_planes; i++) {
+ plane[i] = get_sp_plane(dev, test_crtc);
+ if (!plane[i]) {
+ printf("no unused planes available\n");
+ goto out;
+ }
+
+ plane[i]->bo = create_sp_bo(dev, plane_w, plane_h, 16, plane[i]->format, 0);
+ if (!plane[i]->bo) {
+ printf("failed to create plane bo\n");
+ goto out;
+ }
+
+ fill_bo(plane[i]->bo, 0xFF, 0xFF, 0xFF, 0xFF);
+ }
+
+ pset = drmModeAtomicAlloc();
+ if (!pset) {
+ printf("Failed to allocate the property set\n");
+ goto out;
+ }
+
+ while (!terminate) {
+ FD_ZERO(&fds);
+ FD_SET(dev->fd, &fds);
+
+ incrementor(&x_inc, &x, 5, 0,
+ test_crtc->crtc->mode.hdisplay - plane_w);
+ incrementor(&y_inc, &y, 5, 0, test_crtc->crtc->mode.vdisplay -
+ plane_h * num_test_planes);
+
+ for (j = 0; j < num_test_planes; j++) {
+ ret = set_sp_plane_pset(dev, plane[j], pset, test_crtc,
+ x, y + j * plane_h);
+ if (ret) {
+ printf("failed to move plane %d\n", ret);
+ goto out;
+ }
+ }
+
+ ret = drmModeAtomicCommit(dev->fd, pset,
+ DRM_MODE_PAGE_FLIP_EVENT, NULL);
+ if (ret) {
+ printf("failed to commit properties ret=%d\n", ret);
+ goto out;
+ }
+
+ do {
+ ret = select(dev->fd + 1, &fds, NULL, NULL, NULL);
+ } while (ret == -1 && errno == EINTR);
+
+ if (FD_ISSET(dev->fd, &fds))
+ drmHandleEvent(dev->fd, &event_context);
+ }
+
+ drmModeAtomicFree(pset);
+
+ for (i = 0; i < num_test_planes; i++)
+ put_sp_plane(plane[i]);
+
+out:
+ destroy_sp_dev(dev);
+ free(plane);
+ return ret;
+}
diff --git a/tests/planetest/bo.c b/tests/planetest/bo.c
new file mode 100644
index 0000000..d4b82c6
--- /dev/null
+++ b/tests/planetest/bo.c
@@ -0,0 +1,234 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+#include <errno.h>
+
+#include <xf86drm.h>
+#include <xf86drmMode.h>
+#include <drm_fourcc.h>
+
+#include "bo.h"
+#include "dev.h"
+
+#define MAKE_YUV_601_Y(r, g, b) \
+ ((( 66 * (r) + 129 * (g) + 25 * (b) + 128) >> 8) + 16)
+#define MAKE_YUV_601_U(r, g, b) \
+ (((-38 * (r) - 74 * (g) + 112 * (b) + 128) >> 8) + 128)
+#define MAKE_YUV_601_V(r, g, b) \
+ (((112 * (r) - 94 * (g) - 18 * (b) + 128) >> 8) + 128)
+
+static void draw_rect_yuv(struct sp_bo *bo, uint32_t x, uint32_t y, uint32_t width,
+ uint32_t height, uint8_t a, uint8_t r, uint8_t g, uint8_t b)
+{
+ uint32_t i, j, xmax = x + width, ymax = y + height;
+
+ if (xmax > bo->width)
+ xmax = bo->width;
+ if (ymax > bo->height)
+ ymax = bo->height;
+
+ for (i = y; i < ymax; i++) {
+ uint8_t *luma = bo->map_addr + i * bo->pitch;
+
+ for (j = x; j < xmax; j++)
+ luma[j] = MAKE_YUV_601_Y(r, g, b);
+ }
+
+ for (i = y; i < ymax / 2; i++) {
+ uint8_t *chroma = bo->map_addr + (i + height) * bo->pitch;
+
+ for (j = x; j < xmax / 2; j++) {
+ chroma[j*2] = MAKE_YUV_601_U(r, g, b);
+ chroma[j*2 + 1] = MAKE_YUV_601_V(r, g, b);
+ }
+ }
+}
+
+void fill_bo(struct sp_bo *bo, uint8_t a, uint8_t r, uint8_t g, uint8_t b)
+{
+ if (bo->format == DRM_FORMAT_NV12)
+ draw_rect_yuv(bo, 0, 0, bo->width, bo->height, a, r, g, b);
+ else
+ draw_rect(bo, 0, 0, bo->width, bo->height, a, r, g, b);
+}
+
+void draw_rect(struct sp_bo *bo, uint32_t x, uint32_t y, uint32_t width,
+ uint32_t height, uint8_t a, uint8_t r, uint8_t g, uint8_t b)
+{
+ uint32_t i, j, xmax = x + width, ymax = y + height;
+
+ if (xmax > bo->width)
+ xmax = bo->width;
+ if (ymax > bo->height)
+ ymax = bo->height;
+
+ for (i = y; i < ymax; i++) {
+ uint8_t *row = bo->map_addr + i * bo->pitch;
+
+ for (j = x; j < xmax; j++) {
+ uint8_t *pixel = row + j * 4;
+
+ if (bo->format == DRM_FORMAT_ARGB8888 ||
+ bo->format == DRM_FORMAT_XRGB8888)
+ {
+ pixel[0] = b;
+ pixel[1] = g;
+ pixel[2] = r;
+ pixel[3] = a;
+ } else if (bo->format == DRM_FORMAT_RGBA8888) {
+ pixel[0] = r;
+ pixel[1] = g;
+ pixel[2] = b;
+ pixel[3] = a;
+ }
+ }
+ }
+}
+
+static int add_fb_sp_bo(struct sp_bo *bo, uint32_t format)
+{
+ int ret;
+ uint32_t handles[4], pitches[4], offsets[4];
+
+ handles[0] = bo->handle;
+ pitches[0] = bo->pitch;
+ offsets[0] = 0;
+ if (bo->format == DRM_FORMAT_NV12) {
+ handles[1] = bo->handle;
+ pitches[1] = pitches[0];
+ offsets[1] = pitches[0] * bo->height;
+ }
+
+ ret = drmModeAddFB2(bo->dev->fd, bo->width, bo->height,
+ format, handles, pitches, offsets,
+ &bo->fb_id, bo->flags);
+ if (ret) {
+ printf("failed to create fb ret=%d\n", ret);
+ return ret;
+ }
+ return 0;
+}
+
+static int map_sp_bo(struct sp_bo *bo)
+{
+ int ret;
+ struct drm_mode_map_dumb md;
+
+ if (bo->map_addr)
+ return 0;
+
+ md.handle = bo->handle;
+ ret = drmIoctl(bo->dev->fd, DRM_IOCTL_MODE_MAP_DUMB, &md);
+ if (ret) {
+ printf("failed to map sp_bo ret=%d\n", ret);
+ return ret;
+ }
+
+ bo->map_addr = mmap(NULL, bo->size, PROT_READ | PROT_WRITE, MAP_SHARED,
+ bo->dev->fd, md.offset);
+ if (bo->map_addr == MAP_FAILED) {
+ printf("failed to map bo ret=%d\n", -errno);
+ return -errno;
+ }
+ return 0;
+}
+
+static int format_to_bpp(uint32_t format)
+{
+ switch (format) {
+ case DRM_FORMAT_NV12:
+ return 8;
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_RGBA8888:
+ default:
+ return 32;
+ }
+}
+
+struct sp_bo *create_sp_bo(struct sp_dev *dev, uint32_t width, uint32_t height,
+ uint32_t depth, uint32_t format, uint32_t flags)
+{
+ int ret;
+ struct drm_mode_create_dumb cd;
+ struct sp_bo *bo;
+
+ bo = calloc(1, sizeof(*bo));
+ if (!bo)
+ return NULL;
+
+ if (format == DRM_FORMAT_NV12)
+ cd.height = height * 3 / 2;
+ else
+ cd.height = height;
+
+ cd.width = width;
+ cd.bpp = format_to_bpp(format);
+ cd.flags = flags;
+
+ ret = drmIoctl(dev->fd, DRM_IOCTL_MODE_CREATE_DUMB, &cd);
+ if (ret) {
+ printf("failed to create sp_bo %d\n", ret);
+ goto err;
+ }
+
+ bo->dev = dev;
+ bo->width = width;
+ bo->height = height;
+ bo->depth = depth;
+ bo->bpp = format_to_bpp(format);
+ bo->format = format;
+ bo->flags = flags;
+
+ bo->handle = cd.handle;
+ bo->pitch = cd.pitch;
+ bo->size = cd.size;
+
+ ret = add_fb_sp_bo(bo, format);
+ if (ret) {
+ printf("failed to add fb ret=%d\n", ret);
+ goto err;
+ }
+
+ ret = map_sp_bo(bo);
+ if (ret) {
+ printf("failed to map bo ret=%d\n", ret);
+ goto err;
+ }
+
+ return bo;
+
+err:
+ free_sp_bo(bo);
+ return NULL;
+}
+
+void free_sp_bo(struct sp_bo *bo)
+{
+ int ret;
+ struct drm_mode_destroy_dumb dd;
+
+ if (!bo)
+ return;
+
+ if (bo->map_addr)
+ munmap(bo->map_addr, bo->size);
+
+ if (bo->fb_id) {
+ ret = drmModeRmFB(bo->dev->fd, bo->fb_id);
+ if (ret)
+ printf("Failed to rmfb ret=%d!\n", ret);
+ }
+
+ if (bo->handle) {
+ dd.handle = bo->handle;
+ ret = drmIoctl(bo->dev->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &dd);
+ if (ret)
+ printf("Failed to destroy buffer ret=%d\n", ret);
+ }
+
+ free(bo);
+}
diff --git a/tests/planetest/bo.h b/tests/planetest/bo.h
new file mode 100644
index 0000000..7471e12
--- /dev/null
+++ b/tests/planetest/bo.h
@@ -0,0 +1,34 @@
+#ifndef __BO_H_INCLUDED__
+#define __BO_H_INCLUDED__
+
+#include <stdint.h>
+
+struct sp_dev;
+
+struct sp_bo {
+ struct sp_dev *dev;
+
+ uint32_t width;
+ uint32_t height;
+ uint32_t depth;
+ uint32_t bpp;
+ uint32_t format;
+ uint32_t flags;
+
+ uint32_t fb_id;
+ uint32_t handle;
+ void *map_addr;
+ uint32_t pitch;
+ uint32_t size;
+};
+
+struct sp_bo *create_sp_bo(struct sp_dev *dev, uint32_t width, uint32_t height,
+ uint32_t depth, uint32_t format, uint32_t flags);
+
+void fill_bo(struct sp_bo *bo, uint8_t a, uint8_t r, uint8_t g, uint8_t b);
+void draw_rect(struct sp_bo *bo, uint32_t x, uint32_t y, uint32_t width,
+ uint32_t height, uint8_t a, uint8_t r, uint8_t g, uint8_t b);
+
+void free_sp_bo(struct sp_bo *bo);
+
+#endif /* __BO_H_INCLUDED__ */
diff --git a/tests/planetest/dev.c b/tests/planetest/dev.c
new file mode 100644
index 0000000..bd0968c
--- /dev/null
+++ b/tests/planetest/dev.c
@@ -0,0 +1,367 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+#include <getopt.h>
+
+#include <drm.h>
+#include <drm_fourcc.h>
+#include <errno.h>
+#include <xf86drm.h>
+#include <xf86drmMode.h>
+
+#include "bo.h"
+#include "dev.h"
+#include "modeset.h"
+
+static void show_usage(char *name)
+{
+ printf("Usage: %s [OPTION]\n", name);
+ printf(" -c, --card Index of dri card (ie: /dev/dri/cardN)\n");
+ printf(" -r, --crtc Index of crtc to use for test\n");
+ printf("\n\n");
+}
+
+void parse_arguments(int argc, char *argv[], int *card, int *crtc)
+{
+ static struct option options[] = {
+ { "card", required_argument, NULL, 'c' },
+ { "crtc", required_argument, NULL, 'r' },
+ { "help", no_argument, NULL, 'h' },
+ };
+ int option_index = 0;
+ int c;
+
+ *card = -1;
+ *crtc = -1;
+ do {
+ c = getopt_long(argc, argv, "c:r:h", options, &option_index);
+ switch (c) {
+ case 0:
+ case 'h':
+ show_usage(argv[0]);
+ exit(0);
+ case -1:
+ break;
+ case 'c':
+ if (optarg[0] < '0' || optarg[0] > '9') {
+ printf("Invalid card value '%s'!\n", optarg);
+ show_usage(argv[0]);
+ exit(-1);
+ }
+ *card = optarg[0] - '0';
+ break;
+ case 'r':
+ if (optarg[0] < '0' || optarg[0] > '9') {
+ printf("Invalid crtc value '%s'!\n", optarg);
+ show_usage(argv[0]);
+ exit(-1);
+ }
+ *crtc = optarg[0] - '0';
+ break;
+ }
+ } while (c != -1);
+
+ if (*card < 0 || *crtc < 0) {
+ show_usage(argv[0]);
+ exit(-1);
+ }
+}
+
+static uint32_t get_prop_id(struct sp_dev *dev,
+ drmModeObjectPropertiesPtr props, const char *name)
+{
+ drmModePropertyPtr p;
+ uint32_t i, prop_id = 0; /* Property ID should always be > 0 */
+
+ for (i = 0; !prop_id && i < props->count_props; i++) {
+ p = drmModeGetProperty(dev->fd, props->props[i]);
+ if (!strcmp(p->name, name))
+ prop_id = p->prop_id;
+ drmModeFreeProperty(p);
+ }
+ if (!prop_id)
+ printf("Could not find %s property\n", name);
+ return prop_id;
+}
+
+static int get_supported_format(struct sp_plane *plane, uint32_t *format)
+{
+ uint32_t i;
+
+ for (i = 0; i < plane->plane->count_formats; i++) {
+ if (plane->plane->formats[i] == DRM_FORMAT_XRGB8888 ||
+ plane->plane->formats[i] == DRM_FORMAT_ARGB8888 ||
+ plane->plane->formats[i] == DRM_FORMAT_RGBA8888 ||
+ plane->plane->formats[i] == DRM_FORMAT_NV12) {
+ *format = plane->plane->formats[i];
+ return 0;
+ }
+ }
+ printf("No suitable formats found!\n");
+ return -ENOENT;
+}
+
+struct sp_dev *create_sp_dev(int card)
+{
+ struct sp_dev *dev;
+ int ret, fd, i, j;
+ drmModeRes *r = NULL;
+ drmModePlaneRes *pr = NULL;
+ char card_path[256];
+
+ snprintf(card_path, sizeof(card_path), "/dev/dri/card%d", card);
+
+ fd = open(card_path, O_RDWR);
+ if (fd < 0) {
+ printf("failed to open card0\n");
+ return NULL;
+ }
+
+ dev = calloc(1, sizeof(*dev));
+ if (!dev) {
+ printf("failed to allocate dev\n");
+ return NULL;
+ }
+
+ dev->fd = fd;
+
+ ret = drmSetClientCap(dev->fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
+ if (ret) {
+ printf("failed to set client cap\n");
+ goto err;
+ }
+
+ ret = drmSetClientCap(dev->fd, DRM_CLIENT_CAP_ATOMIC, 1);
+ if (ret) {
+ printf("Failed to set atomic cap %d", ret);
+ goto err;
+ }
+
+ r = drmModeGetResources(dev->fd);
+ if (!r) {
+ printf("failed to get r\n");
+ goto err;
+ }
+
+ dev->num_connectors = r->count_connectors;
+ dev->connectors = calloc(dev->num_connectors,
+ sizeof(struct sp_connector));
+ if (!dev->connectors) {
+ printf("failed to allocate connectors\n");
+ goto err;
+ }
+ for (i = 0; i < dev->num_connectors; i++) {
+ drmModeObjectPropertiesPtr props;
+ dev->connectors[i].conn = drmModeGetConnector(dev->fd,
+ r->connectors[i]);
+ if (!dev->connectors[i].conn) {
+ printf("failed to get connector %d\n", i);
+ goto err;
+ }
+
+ props = drmModeObjectGetProperties(dev->fd, r->connectors[i],
+ DRM_MODE_OBJECT_CONNECTOR);
+ if (!props) {
+ printf("failed to get connector properties\n");
+ goto err;
+ }
+
+ dev->connectors[i].crtc_id_pid = get_prop_id(dev, props,
+ "CRTC_ID");
+ drmModeFreeObjectProperties(props);
+ if (!dev->connectors[i].crtc_id_pid)
+ goto err;
+ }
+
+ dev->num_encoders = r->count_encoders;
+ dev->encoders = calloc(dev->num_encoders, sizeof(*dev->encoders));
+ if (!dev->encoders) {
+ printf("failed to allocate encoders\n");
+ goto err;
+ }
+ for (i = 0; i < dev->num_encoders; i++) {
+ dev->encoders[i] = drmModeGetEncoder(dev->fd, r->encoders[i]);
+ if (!dev->encoders[i]) {
+ printf("failed to get encoder %d\n", i);
+ goto err;
+ }
+ }
+
+ dev->num_crtcs = r->count_crtcs;
+ dev->crtcs = calloc(dev->num_crtcs, sizeof(struct sp_crtc));
+ if (!dev->crtcs) {
+ printf("failed to allocate crtcs\n");
+ goto err;
+ }
+ for (i = 0; i < dev->num_crtcs; i++) {
+ drmModeObjectPropertiesPtr props;
+
+ dev->crtcs[i].crtc = drmModeGetCrtc(dev->fd, r->crtcs[i]);
+ if (!dev->crtcs[i].crtc) {
+ printf("failed to get crtc %d\n", i);
+ goto err;
+ }
+ dev->crtcs[i].pipe = i;
+ dev->crtcs[i].num_planes = 0;
+
+ props = drmModeObjectGetProperties(dev->fd, r->crtcs[i],
+ DRM_MODE_OBJECT_CRTC);
+ if (!props) {
+ printf("failed to get crtc properties\n");
+ goto err;
+ }
+
+ dev->crtcs[i].mode_pid = get_prop_id(dev, props, "MODE_ID");
+ dev->crtcs[i].active_pid = get_prop_id(dev, props, "ACTIVE");
+ drmModeFreeObjectProperties(props);
+ if (!dev->crtcs[i].mode_pid || !dev->crtcs[i].active_pid)
+ goto err;
+ }
+
+ pr = drmModeGetPlaneResources(dev->fd);
+ if (!pr) {
+ printf("failed to get plane resources\n");
+ goto err;
+ }
+ dev->num_planes = pr->count_planes;
+ dev->planes = calloc(dev->num_planes, sizeof(struct sp_plane));
+ for(i = 0; i < dev->num_planes; i++) {
+ drmModeObjectPropertiesPtr props;
+ struct sp_plane *plane = &dev->planes[i];
+
+ plane->dev = dev;
+ plane->plane = drmModeGetPlane(dev->fd, pr->planes[i]);
+ if (!plane->plane) {
+ printf("failed to get plane %d\n", i);
+ goto err;
+ }
+ plane->bo = NULL;
+ plane->in_use = 0;
+
+ ret = get_supported_format(plane, &plane->format);
+ if (ret) {
+ printf("failed to get supported format: %d\n", ret);
+ goto err;
+ }
+
+ for (j = 0; j < dev->num_crtcs; j++) {
+ if (plane->plane->possible_crtcs & (1 << j))
+ dev->crtcs[j].num_planes++;
+ }
+
+ props = drmModeObjectGetProperties(dev->fd, pr->planes[i],
+ DRM_MODE_OBJECT_PLANE);
+ if (!props) {
+ printf("failed to get plane properties\n");
+ goto err;
+ }
+ plane->crtc_pid = get_prop_id(dev, props, "CRTC_ID");
+ if (!plane->crtc_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->fb_pid = get_prop_id(dev, props, "FB_ID");
+ if (!plane->fb_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->crtc_x_pid = get_prop_id(dev, props, "CRTC_X");
+ if (!plane->crtc_x_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->crtc_y_pid = get_prop_id(dev, props, "CRTC_Y");
+ if (!plane->crtc_y_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->crtc_w_pid = get_prop_id(dev, props, "CRTC_W");
+ if (!plane->crtc_w_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->crtc_h_pid = get_prop_id(dev, props, "CRTC_H");
+ if (!plane->crtc_h_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->src_x_pid = get_prop_id(dev, props, "SRC_X");
+ if (!plane->src_x_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->src_y_pid = get_prop_id(dev, props, "SRC_Y");
+ if (!plane->src_y_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->src_w_pid = get_prop_id(dev, props, "SRC_W");
+ if (!plane->src_w_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ plane->src_h_pid = get_prop_id(dev, props, "SRC_H");
+ if (!plane->src_h_pid) {
+ drmModeFreeObjectProperties(props);
+ goto err;
+ }
+ drmModeFreeObjectProperties(props);
+ }
+
+ if (pr)
+ drmModeFreePlaneResources(pr);
+ if (r)
+ drmModeFreeResources(r);
+
+ return dev;
+err:
+ if (pr)
+ drmModeFreePlaneResources(pr);
+ if (r)
+ drmModeFreeResources(r);
+ destroy_sp_dev(dev);
+ return NULL;
+}
+
+void destroy_sp_dev(struct sp_dev *dev)
+{
+ int i;
+
+ if (dev->planes) {
+ for (i = 0; i< dev->num_planes; i++) {
+ if (dev->planes[i].in_use)
+ put_sp_plane(&dev->planes[i]);
+ if (dev->planes[i].plane)
+ drmModeFreePlane(dev->planes[i].plane);
+ if (dev->planes[i].bo)
+ free_sp_bo(dev->planes[i].bo);
+ }
+ free(dev->planes);
+ }
+ if (dev->crtcs) {
+ for (i = 0; i< dev->num_crtcs; i++) {
+ if (dev->crtcs[i].crtc)
+ drmModeFreeCrtc(dev->crtcs[i].crtc);
+ }
+ free(dev->crtcs);
+ }
+ if (dev->encoders) {
+ for (i = 0; i< dev->num_encoders; i++) {
+ if (dev->encoders[i])
+ drmModeFreeEncoder(dev->encoders[i]);
+ }
+ free(dev->encoders);
+ }
+ if (dev->connectors) {
+ for (i = 0; i< dev->num_connectors; i++) {
+ if (dev->connectors[i].conn)
+ drmModeFreeConnector(dev->connectors[i].conn);
+ }
+ free(dev->connectors);
+ }
+
+ close(dev->fd);
+ free(dev);
+}
diff --git a/tests/planetest/dev.h b/tests/planetest/dev.h
new file mode 100644
index 0000000..04dec79
--- /dev/null
+++ b/tests/planetest/dev.h
@@ -0,0 +1,65 @@
+#ifndef __DEV_H_INCLUDED__
+#define __DEV_H_INCLUDED__
+
+#include <stdint.h>
+#include <xf86drmMode.h>
+
+struct sp_bo;
+struct sp_dev;
+
+struct sp_plane {
+ struct sp_dev *dev;
+ drmModePlanePtr plane;
+ struct sp_bo *bo;
+ int in_use;
+ uint32_t format;
+
+ /* Property ID's */
+ uint32_t crtc_pid;
+ uint32_t fb_pid;
+ uint32_t zpos_pid;
+ uint32_t crtc_x_pid;
+ uint32_t crtc_y_pid;
+ uint32_t crtc_w_pid;
+ uint32_t crtc_h_pid;
+ uint32_t src_x_pid;
+ uint32_t src_y_pid;
+ uint32_t src_w_pid;
+ uint32_t src_h_pid;
+};
+
+struct sp_connector {
+ drmModeConnectorPtr conn;
+ uint32_t crtc_id_pid;
+};
+
+struct sp_crtc {
+ drmModeCrtcPtr crtc;
+ int pipe;
+ int num_planes;
+ uint32_t mode_pid;
+ uint32_t active_pid;
+};
+
+struct sp_dev {
+ int fd;
+
+ int num_connectors;
+ struct sp_connector *connectors;
+
+ int num_encoders;
+ drmModeEncoderPtr *encoders;
+
+ int num_crtcs;
+ struct sp_crtc *crtcs;
+
+ int num_planes;
+ struct sp_plane *planes;
+};
+
+void parse_arguments(int argc, char *argv[], int *card, int *crtc);
+
+struct sp_dev *create_sp_dev(int card);
+void destroy_sp_dev(struct sp_dev *dev);
+
+#endif /* __DEV_H_INCLUDED__ */
diff --git a/tests/planetest/modeset.c b/tests/planetest/modeset.c
new file mode 100644
index 0000000..b8f6690
--- /dev/null
+++ b/tests/planetest/modeset.c
@@ -0,0 +1,232 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <xf86drm.h>
+#include <xf86drmMode.h>
+#include <drm_fourcc.h>
+
+#include "modeset.h"
+#include "bo.h"
+#include "dev.h"
+
+static int set_crtc_mode(struct sp_dev *dev, struct sp_crtc *crtc,
+ struct sp_connector *conn, drmModeModeInfoPtr mode)
+{
+ int ret;
+ struct drm_mode_create_blob create_blob;
+ drmModeAtomicReqPtr pset;
+
+ memset(&create_blob, 0, sizeof(create_blob));
+ create_blob.length = sizeof(struct drm_mode_modeinfo);
+ create_blob.data = (__u64)(uintptr_t)mode;
+
+ ret = drmIoctl(dev->fd, DRM_IOCTL_MODE_CREATEPROPBLOB, &create_blob);
+ if (ret) {
+ printf("Failed to create mode property blob %d", ret);
+ return ret;
+ }
+
+ pset = drmModeAtomicAlloc();
+ if (!pset) {
+ printf("Failed to allocate property set");
+ return -1;
+ }
+
+ ret = drmModeAtomicAddProperty(pset, crtc->crtc->crtc_id,
+ crtc->mode_pid, create_blob.blob_id) ||
+ drmModeAtomicAddProperty(pset, crtc->crtc->crtc_id,
+ crtc->active_pid, 1) ||
+ drmModeAtomicAddProperty(pset, conn->conn->connector_id,
+ conn->crtc_id_pid, crtc->crtc->crtc_id);
+ if (ret) {
+ printf("Failed to add blob %d to pset", create_blob.blob_id);
+ drmModeAtomicFree(pset);
+ return ret;
+ }
+
+ ret = drmModeAtomicCommit(dev->fd, pset, DRM_MODE_ATOMIC_ALLOW_MODESET,
+ NULL);
+
+ drmModeAtomicFree(pset);
+
+ if (ret) {
+ printf("Failed to commit pset ret=%d\n", ret);
+ return ret;
+ }
+
+ memcpy(&crtc->crtc->mode, mode, sizeof(struct drm_mode_modeinfo));
+ crtc->crtc->mode_valid = 1;
+ return 0;
+}
+
+int initialize_screens(struct sp_dev *dev)
+{
+ int ret, i, j;
+ unsigned crtc_mask = 0;
+
+ for (i = 0; i < dev->num_connectors; i++) {
+ struct sp_connector *c = &dev->connectors[i];
+ drmModeModeInfoPtr m = NULL;
+ drmModeEncoderPtr e = NULL;
+ struct sp_crtc *cr = NULL;
+
+ if (c->conn->connection != DRM_MODE_CONNECTED)
+ continue;
+
+ if (!c->conn->count_modes) {
+ printf("connector has no modes, skipping\n");
+ continue;
+ }
+
+ /* Take the first unless there's a preferred mode */
+ m = &c->conn->modes[0];
+ for (j = 0; j < c->conn->count_modes; j++) {
+ drmModeModeInfoPtr tmp_m = &c->conn->modes[j];
+
+ if (!(tmp_m->type & DRM_MODE_TYPE_PREFERRED))
+ continue;
+
+ m = tmp_m;
+ break;
+ }
+
+ if (!c->conn->count_encoders) {
+ printf("no possible encoders for connector\n");
+ continue;
+ }
+
+ for (j = 0; j < dev->num_encoders; j++) {
+ e = dev->encoders[j];
+ if (e->encoder_id == c->conn->encoders[0])
+ break;
+ }
+ if (j == dev->num_encoders) {
+ printf("could not find encoder for the connector\n");
+ continue;
+ }
+
+ for (j = 0; j < dev->num_crtcs; j++) {
+ if ((1 << j) & crtc_mask)
+ continue;
+
+ cr = &dev->crtcs[j];
+
+ if ((1 << j) & e->possible_crtcs)
+ break;
+ }
+ if (j == dev->num_crtcs) {
+ printf("could not find crtc for the encoder\n");
+ continue;
+ }
+
+ ret = set_crtc_mode(dev, cr, c, m);
+ if (ret) {
+ printf("failed to set mode!\n");
+ continue;
+ }
+ crtc_mask |= 1 << j;
+ }
+ return 0;
+}
+
+struct sp_plane *get_sp_plane(struct sp_dev *dev, struct sp_crtc *crtc)
+{
+ int i;
+
+ for(i = 0; i < dev->num_planes; i++) {
+ struct sp_plane *p = &dev->planes[i];
+
+ if (p->in_use)
+ continue;
+
+ if (!(p->plane->possible_crtcs & (1 << crtc->pipe)))
+ continue;
+
+ p->in_use = 1;
+ return p;
+ }
+ return NULL;
+}
+
+void put_sp_plane(struct sp_plane *plane)
+{
+ drmModePlanePtr p;
+
+ /* Get the latest plane information (most notably the crtc_id) */
+ p = drmModeGetPlane(plane->dev->fd, plane->plane->plane_id);
+ if (p)
+ plane->plane = p;
+
+ if (plane->bo) {
+ free_sp_bo(plane->bo);
+ plane->bo = NULL;
+ }
+ plane->in_use = 0;
+}
+
+int set_sp_plane(struct sp_dev *dev, struct sp_plane *plane,
+ struct sp_crtc *crtc, int x, int y)
+{
+ int ret;
+ uint32_t w, h;
+
+ w = plane->bo->width;
+ h = plane->bo->height;
+
+ if ((w + x) > crtc->crtc->mode.hdisplay)
+ w = crtc->crtc->mode.hdisplay - x;
+ if ((h + y) > crtc->crtc->mode.vdisplay)
+ h = crtc->crtc->mode.vdisplay - y;
+
+ ret = drmModeSetPlane(dev->fd, plane->plane->plane_id,
+ crtc->crtc->crtc_id, plane->bo->fb_id, 0, x, y, w, h,
+ 0, 0, w << 16, h << 16);
+ if (ret) {
+ printf("failed to set plane to crtc ret=%d\n", ret);
+ return ret;
+ }
+
+ return ret;
+}
+int set_sp_plane_pset(struct sp_dev *dev, struct sp_plane *plane,
+ drmModeAtomicReqPtr pset, struct sp_crtc *crtc, int x, int y)
+{
+ int ret;
+ uint32_t w, h;
+
+ w = plane->bo->width;
+ h = plane->bo->height;
+
+ if ((w + x) > crtc->crtc->mode.hdisplay)
+ w = crtc->crtc->mode.hdisplay - x;
+ if ((h + y) > crtc->crtc->mode.vdisplay)
+ h = crtc->crtc->mode.vdisplay - y;
+
+ ret = drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->crtc_pid, crtc->crtc->crtc_id)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->fb_pid, plane->bo->fb_id)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->crtc_x_pid, x)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->crtc_y_pid, y)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->crtc_w_pid, w)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->crtc_h_pid, h)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->src_x_pid, 0)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->src_y_pid, 0)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->src_w_pid, w << 16)
+ || drmModeAtomicAddProperty(pset, plane->plane->plane_id,
+ plane->src_h_pid, h << 16);
+ if (ret) {
+ printf("failed to add properties to the set\n");
+ return -1;
+ }
+
+ return ret;
+}
diff --git a/tests/planetest/modeset.h b/tests/planetest/modeset.h
new file mode 100644
index 0000000..5499959
--- /dev/null
+++ b/tests/planetest/modeset.h
@@ -0,0 +1,19 @@
+#ifndef __MODESET_H_INCLUDED__
+#define __MODESET_H_INCLUDED__
+
+struct sp_dev;
+struct sp_crtc;
+
+int initialize_screens(struct sp_dev *dev);
+
+
+struct sp_plane *get_sp_plane(struct sp_dev *dev, struct sp_crtc *crtc);
+void put_sp_plane(struct sp_plane *plane);
+
+int set_sp_plane(struct sp_dev *dev, struct sp_plane *plane,
+ struct sp_crtc *crtc, int x, int y);
+
+int set_sp_plane_pset(struct sp_dev *dev, struct sp_plane *plane,
+ drmModeAtomicReqPtr pset, struct sp_crtc *crtc, int x, int y);
+
+#endif /* __MODESET_H_INCLUDED__ */
diff --git a/tests/planetest/planetest.c b/tests/planetest/planetest.c
new file mode 100644
index 0000000..5e187c9
--- /dev/null
+++ b/tests/planetest/planetest.c
@@ -0,0 +1,116 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/select.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <string.h>
+#include <signal.h>
+#include <time.h>
+#include <errno.h>
+
+#include <xf86drm.h>
+
+#include "dev.h"
+#include "bo.h"
+#include "modeset.h"
+
+static int terminate = 0;
+
+static void sigint_handler(int arg)
+{
+ terminate = 1;
+}
+
+static void incrementor(int *inc, int *val, int increment, int lower, int upper)
+{
+ if(*inc > 0)
+ *inc = *val + increment >= upper ? -1 : 1;
+ else
+ *inc = *val - increment <= lower ? 1 : -1;
+ *val += *inc * increment;
+}
+
+int main(int argc, char *argv[])
+{
+ int ret, i, j, num_test_planes;
+ int x_inc = 1, x = 0, y_inc = 1, y = 0;
+ uint32_t plane_w = 128, plane_h = 128;
+ struct sp_dev *dev;
+ struct sp_plane **plane = NULL;
+ struct sp_crtc *test_crtc;
+ int card = 0, crtc = 0;
+
+ signal(SIGINT, sigint_handler);
+
+ parse_arguments(argc, argv, &card, &crtc);
+
+ dev = create_sp_dev(card);
+ if (!dev) {
+ printf("Failed to create sp_dev\n");
+ return -1;
+ }
+
+ if (crtc >= dev->num_crtcs) {
+ printf("Invalid crtc %d (num=%d)\n", crtc, dev->num_crtcs);
+ return -1;
+ }
+
+ ret = initialize_screens(dev);
+ if (ret) {
+ printf("Failed to initialize screens\n");
+ goto out;
+ }
+ test_crtc = &dev->crtcs[crtc];
+
+ plane = calloc(dev->num_planes, sizeof(*plane));
+ if (!plane) {
+ printf("Failed to allocate plane array\n");
+ goto out;
+ }
+
+ /* Create our planes */
+ num_test_planes = test_crtc->num_planes;
+ for (i = 0; i < num_test_planes; i++) {
+ plane[i] = get_sp_plane(dev, test_crtc);
+ if (!plane[i]) {
+ printf("no unused planes available\n");
+ goto out;
+ }
+
+ plane[i]->bo = create_sp_bo(dev, plane_w, plane_h, 16,
+ plane[i]->format, 0);
+ if (!plane[i]->bo) {
+ printf("failed to create plane bo\n");
+ goto out;
+ }
+
+ fill_bo(plane[i]->bo, 0xFF, 0xFF, 0xFF, 0xFF);
+ }
+
+ while (!terminate) {
+ incrementor(&x_inc, &x, 5, 0,
+ test_crtc->crtc->mode.hdisplay - plane_w);
+ incrementor(&y_inc, &y, 5, 0, test_crtc->crtc->mode.vdisplay -
+ plane_h * num_test_planes);
+
+ for (j = 0; j < num_test_planes; j++) {
+ ret = set_sp_plane(dev, plane[j], test_crtc,
+ x, y + j * plane_h);
+ if (ret) {
+ printf("failed to set plane %d %d\n", j, ret);
+ goto out;
+ }
+ }
+ usleep(15 * 1000);
+ }
+
+ for (i = 0; i < num_test_planes; i++)
+ put_sp_plane(plane[i]);
+
+out:
+ destroy_sp_dev(dev);
+ free(plane);
+ return ret;
+}
diff --git a/tests/proptest/Makefile.am b/tests/proptest/Makefile.am
index 33b8705..3fde46b 100644
--- a/tests/proptest/Makefile.am
+++ b/tests/proptest/Makefile.am
@@ -2,7 +2,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/tests \
-I$(top_srcdir)
diff --git a/tests/proptest/meson.build b/tests/proptest/meson.build
index 9c87965..22d7473 100644
--- a/tests/proptest/meson.build
+++ b/tests/proptest/meson.build
@@ -21,7 +21,7 @@
proptest = executable(
'proptest',
files('proptest.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_tests, inc_drm],
link_with : [libdrm, libutil],
install : with_install_tests,
diff --git a/tests/radeon/Makefile.am b/tests/radeon/Makefile.am
index 3d173e3..9da7625 100644
--- a/tests/radeon/Makefile.am
+++ b/tests/radeon/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)
diff --git a/tests/radeon/meson.build b/tests/radeon/meson.build
index bb345b7..9e4f916 100644
--- a/tests/radeon/meson.build
+++ b/tests/radeon/meson.build
@@ -23,5 +23,5 @@
files('rbo.c', 'radeon_ttm.c'),
include_directories : [inc_root, inc_drm],
link_with : libdrm,
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
)
diff --git a/tests/tegra/Makefile.am b/tests/tegra/Makefile.am
index b462a30..8e625c8 100644
--- a/tests/tegra/Makefile.am
+++ b/tests/tegra/Makefile.am
@@ -3,9 +3,7 @@
-I$(top_srcdir)/tegra \
-I$(top_srcdir)
-AM_CFLAGS = \
- $(WARN_CFLAGS) \
- -fvisibility=hidden
+AM_CFLAGS = $(WARN_CFLAGS)
LDADD = \
../../tegra/libdrm_tegra.la \
diff --git a/tests/tegra/meson.build b/tests/tegra/meson.build
index 4f8c54f..9c74ac4 100644
--- a/tests/tegra/meson.build
+++ b/tests/tegra/meson.build
@@ -22,6 +22,6 @@
'openclose',
files('openclose.c'),
include_directories : [inc_root, inc_drm, include_directories('../../tegra')],
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
link_with : [libdrm, libdrm_tegra],
)
diff --git a/tests/ttmtest/src/xf86dristr.h b/tests/ttmtest/src/xf86dristr.h
index 2730d1a..3b43438 100644
--- a/tests/ttmtest/src/xf86dristr.h
+++ b/tests/ttmtest/src/xf86dristr.h
@@ -42,8 +42,8 @@
#define XF86DRINAME "XFree86-DRI"
-/* The DRI version number. This was originally set to be the same as the
- * XFree86 version number. However, this version is really independent of
+/* The DRI version number. This was originally set to be the same of the
+ * XFree86 version number. However, this version is really indepedent of
* the XFree86 version.
*
* Version History:
diff --git a/tests/util/format.c b/tests/util/format.c
index 1ca1b82..15ac5e1 100644
--- a/tests/util/format.c
+++ b/tests/util/format.c
@@ -39,8 +39,6 @@
.yuv = { (order), (xsub), (ysub), (chroma_stride) }
static const struct util_format_info format_info[] = {
- /* Indexed */
- { DRM_FORMAT_C8, "C8" },
/* YUV packed */
{ DRM_FORMAT_UYVY, "UYVY", MAKE_YUV_INFO(YUV_YCbCr | YUV_CY, 2, 2, 2) },
{ DRM_FORMAT_VYUY, "VYUY", MAKE_YUV_INFO(YUV_YCrCb | YUV_CY, 2, 2, 2) },
@@ -93,11 +91,6 @@
{ DRM_FORMAT_RGBX1010102, "RX30", MAKE_RGB_INFO(10, 22, 10, 12, 10, 2, 0, 0) },
{ DRM_FORMAT_BGRA1010102, "BA30", MAKE_RGB_INFO(10, 2, 10, 12, 10, 22, 2, 0) },
{ DRM_FORMAT_BGRX1010102, "BX30", MAKE_RGB_INFO(10, 2, 10, 12, 10, 22, 0, 0) },
- { DRM_FORMAT_XRGB16161616F, "XR4H", MAKE_RGB_INFO(16, 32, 16, 16, 16, 0, 0, 0) },
- { DRM_FORMAT_XBGR16161616F, "XB4H", MAKE_RGB_INFO(16, 0, 16, 16, 16, 32, 0, 0) },
- { DRM_FORMAT_ARGB16161616F, "AR4H", MAKE_RGB_INFO(16, 32, 16, 16, 16, 0, 16, 48) },
- { DRM_FORMAT_ABGR16161616F, "AB4H", MAKE_RGB_INFO(16, 0, 16, 16, 16, 32, 16, 48) },
-
};
uint32_t util_format_fourcc(const char *name)
diff --git a/tests/util/kms.c b/tests/util/kms.c
index dd1bbee..8b3e787 100644
--- a/tests/util/kms.c
+++ b/tests/util/kms.c
@@ -144,9 +144,6 @@
"mediatek",
"meson",
"pl111",
- "stm",
- "sun4i-drm",
- "armada-drm",
};
int util_open(const char *device, const char *module)
diff --git a/tests/util/pattern.c b/tests/util/pattern.c
index 42a0e5c..9fa0a41 100644
--- a/tests/util/pattern.c
+++ b/tests/util/pattern.c
@@ -35,7 +35,6 @@
#include <math.h>
#endif
-#include "common.h"
#include "format.h"
#include "pattern.h"
@@ -61,101 +60,15 @@
.u = MAKE_YUV_601_U(r, g, b), \
.v = MAKE_YUV_601_V(r, g, b) }
-/* This function takes 8-bit color values */
-static inline uint32_t shiftcolor8(const struct util_color_component *comp,
- uint32_t value)
-{
- value &= 0xff;
- /* Fill the low bits with the high bits. */
- value = (value << 8) | value;
- /* Shift down to remove unwanted low bits */
- value = value >> (16 - comp->length);
- /* Shift back up to where the value should be */
- return value << comp->offset;
-}
-
-/* This function takes 10-bit color values */
-static inline uint32_t shiftcolor10(const struct util_color_component *comp,
- uint32_t value)
-{
- value &= 0x3ff;
- /* Fill the low bits with the high bits. */
- value = (value << 6) | (value >> 4);
- /* Shift down to remove unwanted low bits */
- value = value >> (16 - comp->length);
- /* Shift back up to where the value should be */
- return value << comp->offset;
-}
-
-/* This function takes 16-bit color values */
-static inline uint64_t shiftcolor16(const struct util_color_component *comp,
- uint64_t value)
-{
- value &= 0xffff;
- /* Shift down to remove unwanted low bits */
- value = value >> (16 - comp->length);
- /* Shift back up to where the value should be */
- return value << comp->offset;
-}
-
-#define MAKE_RGBA10(rgb, r, g, b, a) \
- (shiftcolor10(&(rgb)->red, (r)) | \
- shiftcolor10(&(rgb)->green, (g)) | \
- shiftcolor10(&(rgb)->blue, (b)) | \
- shiftcolor10(&(rgb)->alpha, (a)))
-
#define MAKE_RGBA(rgb, r, g, b, a) \
- (shiftcolor8(&(rgb)->red, (r)) | \
- shiftcolor8(&(rgb)->green, (g)) | \
- shiftcolor8(&(rgb)->blue, (b)) | \
- shiftcolor8(&(rgb)->alpha, (a)))
+ ((((r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \
+ (((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \
+ (((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \
+ (((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset))
#define MAKE_RGB24(rgb, r, g, b) \
{ .value = MAKE_RGBA(rgb, r, g, b, 0) }
-
-/**
- * Takes a uint16_t, divides by 65536, converts the infinite-precision
- * result to fp16 with round-to-zero.
- *
- * Copied from mesa:src/util/half_float.c
- */
-static uint16_t uint16_div_64k_to_half(uint16_t v)
-{
- /* Zero or subnormal. Set the mantissa to (v << 8) and return. */
- if (v < 4)
- return v << 8;
-
- /* Count the leading 0s in the uint16_t */
- int n = __builtin_clz(v) - 16;
-
- /* Shift the mantissa up so bit 16 is the hidden 1 bit,
- * mask it off, then shift back down to 10 bits
- */
- int m = ( ((uint32_t)v << (n + 1)) & 0xffff ) >> 6;
-
- /* (0{n} 1 X{15-n}) * 2^-16
- * = 1.X * 2^(15-n-16)
- * = 1.X * 2^(14-n - 15)
- * which is the FP16 form with e = 14 - n
- */
- int e = 14 - n;
-
- return (e << 10) | m;
-}
-
-#define MAKE_RGBA8FP16(rgb, r, g, b, a) \
- (shiftcolor16(&(rgb)->red, uint16_div_64k_to_half((r) << 8)) | \
- shiftcolor16(&(rgb)->green, uint16_div_64k_to_half((g) << 8)) | \
- shiftcolor16(&(rgb)->blue, uint16_div_64k_to_half((b) << 8)) | \
- shiftcolor16(&(rgb)->alpha, uint16_div_64k_to_half((a) << 8)))
-
-#define MAKE_RGBA10FP16(rgb, r, g, b, a) \
- (shiftcolor16(&(rgb)->red, uint16_div_64k_to_half((r) << 6)) | \
- shiftcolor16(&(rgb)->green, uint16_div_64k_to_half((g) << 6)) | \
- shiftcolor16(&(rgb)->blue, uint16_div_64k_to_half((b) << 6)) | \
- shiftcolor16(&(rgb)->alpha, uint16_div_64k_to_half((a) << 6)))
-
static void fill_smpte_yuv_planar(const struct util_yuv_info *yuv,
unsigned char *y_mem, unsigned char *u_mem,
unsigned char *v_mem, unsigned int width,
@@ -544,140 +457,6 @@
}
}
-static void fill_smpte_rgb16fp(const struct util_rgb_info *rgb, void *mem,
- unsigned int width, unsigned int height,
- unsigned int stride)
-{
- const uint64_t colors_top[] = {
- MAKE_RGBA8FP16(rgb, 192, 192, 192, 255),/* grey */
- MAKE_RGBA8FP16(rgb, 192, 192, 0, 255), /* yellow */
- MAKE_RGBA8FP16(rgb, 0, 192, 192, 255), /* cyan */
- MAKE_RGBA8FP16(rgb, 0, 192, 0, 255), /* green */
- MAKE_RGBA8FP16(rgb, 192, 0, 192, 255), /* magenta */
- MAKE_RGBA8FP16(rgb, 192, 0, 0, 255), /* red */
- MAKE_RGBA8FP16(rgb, 0, 0, 192, 255), /* blue */
- };
- const uint64_t colors_middle[] = {
- MAKE_RGBA8FP16(rgb, 0, 0, 192, 127), /* blue */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 127), /* black */
- MAKE_RGBA8FP16(rgb, 192, 0, 192, 127), /* magenta */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 127), /* black */
- MAKE_RGBA8FP16(rgb, 0, 192, 192, 127), /* cyan */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 127), /* black */
- MAKE_RGBA8FP16(rgb, 192, 192, 192, 127),/* grey */
- };
- const uint64_t colors_bottom[] = {
- MAKE_RGBA8FP16(rgb, 0, 33, 76, 255), /* in-phase */
- MAKE_RGBA8FP16(rgb, 255, 255, 255, 255),/* super white */
- MAKE_RGBA8FP16(rgb, 50, 0, 106, 255), /* quadrature */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 255), /* black */
- MAKE_RGBA8FP16(rgb, 9, 9, 9, 255), /* 3.5% */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 255), /* 7.5% */
- MAKE_RGBA8FP16(rgb, 29, 29, 29, 255), /* 11.5% */
- MAKE_RGBA8FP16(rgb, 19, 19, 19, 255), /* black */
- };
- unsigned int x;
- unsigned int y;
-
- for (y = 0; y < height * 6 / 9; ++y) {
- for (x = 0; x < width; ++x)
- ((uint64_t *)mem)[x] = colors_top[x * 7 / width];
- mem += stride;
- }
-
- for (; y < height * 7 / 9; ++y) {
- for (x = 0; x < width; ++x)
- ((uint64_t *)mem)[x] = colors_middle[x * 7 / width];
- mem += stride;
- }
-
- for (; y < height; ++y) {
- for (x = 0; x < width * 5 / 7; ++x)
- ((uint64_t *)mem)[x] =
- colors_bottom[x * 4 / (width * 5 / 7)];
- for (; x < width * 6 / 7; ++x)
- ((uint64_t *)mem)[x] =
- colors_bottom[(x - width * 5 / 7) * 3
- / (width / 7) + 4];
- for (; x < width; ++x)
- ((uint64_t *)mem)[x] = colors_bottom[7];
- mem += stride;
- }
-}
-
-static void fill_smpte_c8(void *mem, unsigned int width, unsigned int height,
- unsigned int stride)
-{
- unsigned int x;
- unsigned int y;
-
- for (y = 0; y < height * 6 / 9; ++y) {
- for (x = 0; x < width; ++x)
- ((uint8_t *)mem)[x] = x * 7 / width;
- mem += stride;
- }
-
- for (; y < height * 7 / 9; ++y) {
- for (x = 0; x < width; ++x)
- ((uint8_t *)mem)[x] = 7 + (x * 7 / width);
- mem += stride;
- }
-
- for (; y < height; ++y) {
- for (x = 0; x < width * 5 / 7; ++x)
- ((uint8_t *)mem)[x] =
- 14 + (x * 4 / (width * 5 / 7));
- for (; x < width * 6 / 7; ++x)
- ((uint8_t *)mem)[x] =
- 14 + ((x - width * 5 / 7) * 3
- / (width / 7) + 4);
- for (; x < width; ++x)
- ((uint8_t *)mem)[x] = 14 + 7;
- mem += stride;
- }
-}
-
-void util_smpte_c8_gamma(unsigned size, struct drm_color_lut *lut)
-{
- if (size < 7 + 7 + 8) {
- printf("Error: gamma too small: %d < %d\n", size, 7 + 7 + 8);
- return;
- }
- memset(lut, size * sizeof(struct drm_color_lut), 0);
-
-#define FILL_COLOR(idx, r, g, b) \
- lut[idx].red = (r) << 8; \
- lut[idx].green = (g) << 8; \
- lut[idx].blue = (b) << 8
-
- FILL_COLOR( 0, 192, 192, 192); /* grey */
- FILL_COLOR( 1, 192, 192, 0 ); /* yellow */
- FILL_COLOR( 2, 0, 192, 192); /* cyan */
- FILL_COLOR( 3, 0, 192, 0 ); /* green */
- FILL_COLOR( 4, 192, 0, 192); /* magenta */
- FILL_COLOR( 5, 192, 0, 0 ); /* red */
- FILL_COLOR( 6, 0, 0, 192); /* blue */
-
- FILL_COLOR( 7, 0, 0, 192); /* blue */
- FILL_COLOR( 8, 19, 19, 19 ); /* black */
- FILL_COLOR( 9, 192, 0, 192); /* magenta */
- FILL_COLOR(10, 19, 19, 19 ); /* black */
- FILL_COLOR(11, 0, 192, 192); /* cyan */
- FILL_COLOR(12, 19, 19, 19 ); /* black */
- FILL_COLOR(13, 192, 192, 192); /* grey */
-
- FILL_COLOR(14, 0, 33, 76); /* in-phase */
- FILL_COLOR(15, 255, 255, 255); /* super white */
- FILL_COLOR(16, 50, 0, 106); /* quadrature */
- FILL_COLOR(17, 19, 19, 19); /* black */
- FILL_COLOR(18, 9, 9, 9); /* 3.5% */
- FILL_COLOR(19, 19, 19, 19); /* 7.5% */
- FILL_COLOR(20, 29, 29, 29); /* 11.5% */
- FILL_COLOR(21, 19, 19, 19); /* black */
-
-#undef FILL_COLOR
-}
-
static void fill_smpte(const struct util_format_info *info, void *planes[3],
unsigned int width, unsigned int height,
unsigned int stride)
@@ -685,8 +464,6 @@
unsigned char *u, *v;
switch (info->format) {
- case DRM_FORMAT_C8:
- return fill_smpte_c8(planes[0], width, height, stride);
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YUYV:
@@ -754,13 +531,6 @@
case DRM_FORMAT_BGRX1010102:
return fill_smpte_rgb32(&info->rgb, planes[0],
width, height, stride);
-
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
- return fill_smpte_rgb16fp(&info->rgb, planes[0],
- width, height, stride);
}
}
@@ -789,14 +559,6 @@
case DRM_FORMAT_BGR565:
cairo_format = CAIRO_FORMAT_RGB16_565;
break;
-#if CAIRO_VERSION_MAJOR > 1 || (CAIRO_VERSION_MAJOR == 1 && CAIRO_VERSION_MINOR >= 12)
- case DRM_FORMAT_ARGB2101010:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_ABGR2101010:
- case DRM_FORMAT_XBGR2101010:
- cairo_format = CAIRO_FORMAT_RGB30;
- break;
-#endif
default:
return;
}
@@ -980,32 +742,6 @@
make_pwetty(mem_base, width, height, stride, info->format);
}
-static void fill_tiles_rgb16fp(const struct util_format_info *info, void *mem,
- unsigned int width, unsigned int height,
- unsigned int stride)
-{
- const struct util_rgb_info *rgb = &info->rgb;
- void *mem_base = mem;
- unsigned int x, y;
-
- /* TODO: Give this actual fp16 precision */
- for (y = 0; y < height; ++y) {
- for (x = 0; x < width; ++x) {
- div_t d = div(x+y, width);
- uint32_t rgb32 = 0x00130502 * (d.quot >> 6)
- + 0x000a1120 * (d.rem >> 6);
- uint32_t alpha = ((y < height/2) && (x < width/2)) ? 127 : 255;
- uint64_t color =
- MAKE_RGBA8FP16(rgb, (rgb32 >> 16) & 0xff,
- (rgb32 >> 8) & 0xff, rgb32 & 0xff,
- alpha);
-
- ((uint64_t *)mem)[x] = color;
- }
- mem += stride;
- }
-}
-
static void fill_tiles(const struct util_format_info *info, void *planes[3],
unsigned int width, unsigned int height,
unsigned int stride)
@@ -1080,146 +816,14 @@
case DRM_FORMAT_BGRX1010102:
return fill_tiles_rgb32(info, planes[0],
width, height, stride);
-
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
- return fill_tiles_rgb16fp(info, planes[0],
- width, height, stride);
}
}
-static void fill_plain(const struct util_format_info *info, void *planes[3],
+static void fill_plain(void *planes[3],
unsigned int height,
unsigned int stride)
{
- switch (info->format) {
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
- /* 0x3838 = 0.5273 */
- memset(planes[0], 0x38, stride * height);
- break;
- default:
- memset(planes[0], 0x77, stride * height);
- break;
- }
-}
-
-static void fill_gradient_rgb32(const struct util_rgb_info *rgb,
- void *mem,
- unsigned int width, unsigned int height,
- unsigned int stride)
-{
- int i, j;
-
- for (i = 0; i < height / 2; i++) {
- uint32_t *row = mem;
-
- for (j = 0; j < width / 2; j++) {
- uint32_t value = MAKE_RGBA10(rgb, j & 0x3ff, j & 0x3ff, j & 0x3ff, 0);
- row[2*j] = row[2*j+1] = value;
- }
- mem += stride;
- }
-
- for (; i < height; i++) {
- uint32_t *row = mem;
-
- for (j = 0; j < width / 2; j++) {
- uint32_t value = MAKE_RGBA10(rgb, j & 0x3fc, j & 0x3fc, j & 0x3fc, 0);
- row[2*j] = row[2*j+1] = value;
- }
- mem += stride;
- }
-}
-
-static void fill_gradient_rgb16fp(const struct util_rgb_info *rgb,
- void *mem,
- unsigned int width, unsigned int height,
- unsigned int stride)
-{
- int i, j;
-
- for (i = 0; i < height / 2; i++) {
- uint64_t *row = mem;
-
- for (j = 0; j < width / 2; j++) {
- uint64_t value = MAKE_RGBA10FP16(rgb, j & 0x3ff, j & 0x3ff, j & 0x3ff, 0);
- row[2*j] = row[2*j+1] = value;
- }
- mem += stride;
- }
-
- for (; i < height; i++) {
- uint64_t *row = mem;
-
- for (j = 0; j < width / 2; j++) {
- uint64_t value = MAKE_RGBA10FP16(rgb, j & 0x3fc, j & 0x3fc, j & 0x3fc, 0);
- row[2*j] = row[2*j+1] = value;
- }
- mem += stride;
- }
-}
-
-/* The gradient pattern creates two horizontal gray gradients, split
- * into two halves. The top half has 10bpc precision, the bottom half
- * has 8bpc precision. When using with a 10bpc fb format, there are 3
- * possible outcomes:
- *
- * - Pixel data is encoded as 8bpc to the display, no dithering. This
- * would lead to the top and bottom halves looking identical.
- *
- * - Pixel data is encoded as 8bpc to the display, with dithering. This
- * would lead to there being a visible difference between the two halves,
- * but the top half would look a little speck-y due to the dithering.
- *
- * - Pixel data is encoded at 10bpc+ to the display (which implies
- * the display is able to show this level of depth). This should
- * lead to the top half being a very clean gradient, and visibly different
- * from the bottom half.
- *
- * Once we support additional fb formats, this approach could be extended
- * to distinguish even higher bpc precisions.
- *
- * Note that due to practical size considerations, for the screens
- * where this matters, the pattern actually emits stripes 2-pixels
- * wide for each gradient color. Otherwise the difference may be a bit
- * hard to notice.
- */
-static void fill_gradient(const struct util_format_info *info, void *planes[3],
- unsigned int width, unsigned int height,
- unsigned int stride)
-{
- switch (info->format) {
- case DRM_FORMAT_ARGB8888:
- case DRM_FORMAT_XRGB8888:
- case DRM_FORMAT_ABGR8888:
- case DRM_FORMAT_XBGR8888:
- case DRM_FORMAT_RGBA8888:
- case DRM_FORMAT_RGBX8888:
- case DRM_FORMAT_BGRA8888:
- case DRM_FORMAT_BGRX8888:
- case DRM_FORMAT_ARGB2101010:
- case DRM_FORMAT_XRGB2101010:
- case DRM_FORMAT_ABGR2101010:
- case DRM_FORMAT_XBGR2101010:
- case DRM_FORMAT_RGBA1010102:
- case DRM_FORMAT_RGBX1010102:
- case DRM_FORMAT_BGRA1010102:
- case DRM_FORMAT_BGRX1010102:
- return fill_gradient_rgb32(&info->rgb, planes[0],
- width, height, stride);
-
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ARGB16161616F:
- case DRM_FORMAT_ABGR16161616F:
- return fill_gradient_rgb16fp(&info->rgb, planes[0],
- width, height, stride);
- }
+ memset(planes[0], 0x77, stride * height);
}
/*
@@ -1252,32 +856,10 @@
return fill_smpte(info, planes, width, height, stride);
case UTIL_PATTERN_PLAIN:
- return fill_plain(info, planes, height, stride);
-
- case UTIL_PATTERN_GRADIENT:
- return fill_gradient(info, planes, width, height, stride);
+ return fill_plain(planes, height, stride);
default:
printf("Error: unsupported test pattern %u.\n", pattern);
break;
}
}
-
-static const char *pattern_names[] = {
- [UTIL_PATTERN_TILES] = "tiles",
- [UTIL_PATTERN_SMPTE] = "smpte",
- [UTIL_PATTERN_PLAIN] = "plain",
- [UTIL_PATTERN_GRADIENT] = "gradient",
-};
-
-enum util_fill_pattern util_pattern_enum(const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(pattern_names); i++)
- if (!strcmp(pattern_names[i], name))
- return (enum util_fill_pattern)i;
-
- printf("Error: unsupported test pattern %s.\n", name);
- return UTIL_PATTERN_SMPTE;
-}
diff --git a/tests/util/pattern.h b/tests/util/pattern.h
index ea38caf..d5c4260 100644
--- a/tests/util/pattern.h
+++ b/tests/util/pattern.h
@@ -26,21 +26,14 @@
#ifndef UTIL_PATTERN_H
#define UTIL_PATTERN_H
-#include <drm_mode.h>
-
enum util_fill_pattern {
UTIL_PATTERN_TILES,
UTIL_PATTERN_PLAIN,
UTIL_PATTERN_SMPTE,
- UTIL_PATTERN_GRADIENT,
};
void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern,
void *planes[3], unsigned int width,
unsigned int height, unsigned int stride);
-void util_smpte_c8_gamma(unsigned size, struct drm_color_lut *lut);
-
-enum util_fill_pattern util_pattern_enum(const char *name);
-
#endif /* UTIL_PATTERN_H */
diff --git a/tests/vbltest/Makefile.am b/tests/vbltest/Makefile.am
index b6cd7a4..276afad 100644
--- a/tests/vbltest/Makefile.am
+++ b/tests/vbltest/Makefile.am
@@ -1,6 +1,5 @@
AM_CFLAGS = \
$(WARN_CFLAGS)\
- -fvisibility=hidden \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/tests \
-I$(top_srcdir)
diff --git a/tests/vbltest/meson.build b/tests/vbltest/meson.build
index 6339feb..ae52ab8 100644
--- a/tests/vbltest/meson.build
+++ b/tests/vbltest/meson.build
@@ -21,7 +21,7 @@
vbltest = executable(
'vbltest',
files('vbltest.c'),
- c_args : libdrm_c_args,
+ c_args : warn_c_args,
include_directories : [inc_root, inc_tests, inc_drm],
link_with : [libdrm, libutil],
install : with_install_tests,
diff --git a/util_math.h b/util_math.h
index 35bf451..02b15a8 100644
--- a/util_math.h
+++ b/util_math.h
@@ -29,6 +29,6 @@
#define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C))
#define __align_mask(value, mask) (((value) + (mask)) & ~(mask))
-#define ALIGN(value, alignment) __align_mask(value, (__typeof__(value))((alignment) - 1))
+#define ALIGN(value, alignment) __align_mask(value, (typeof(value))((alignment) - 1))
#endif /*_UTIL_MATH_H_*/
diff --git a/vc4/Makefile.am b/vc4/Makefile.am
index 5f82d04..7e486b4 100644
--- a/vc4/Makefile.am
+++ b/vc4/Makefile.am
@@ -23,7 +23,6 @@
AM_CFLAGS = \
$(WARN_CFLAGS) \
- -fvisibility=hidden \
-I$(top_srcdir) \
$(PTHREADSTUBS_CFLAGS) \
$(VALGRIND_CFLAGS) \
diff --git a/xf86drm.c b/xf86drm.c
index 953fc76..390e1eb 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -59,8 +59,6 @@
#endif
#include <math.h>
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
/* Not all systems have MAP_FAILED defined */
#ifndef MAP_FAILED
#define MAP_FAILED ((void *)-1)
@@ -101,7 +99,7 @@
#define DRM_MAJOR 226 /* Linux */
#endif
-#if defined(__OpenBSD__) || defined(__DragonFly__)
+#ifdef __OpenBSD__
struct drm_pciinfo {
uint16_t domain;
uint8_t bus;
@@ -123,7 +121,7 @@
static drmServerInfoPtr drm_server_info;
-drm_public void drmSetServerInfo(drmServerInfoPtr info)
+void drmSetServerInfo(drmServerInfoPtr info)
{
drm_server_info = info;
}
@@ -143,7 +141,7 @@
return vfprintf(stderr, format, ap);
}
-drm_public void
+void
drmMsg(const char *format, ...)
{
va_list ap;
@@ -163,25 +161,25 @@
static void *drmHashTable = NULL; /* Context switch callbacks */
-drm_public void *drmGetHashTable(void)
+void *drmGetHashTable(void)
{
return drmHashTable;
}
-drm_public void *drmMalloc(int size)
+void *drmMalloc(int size)
{
return calloc(1, size);
}
-drm_public void drmFree(void *pt)
+void drmFree(void *pt)
{
free(pt);
}
/**
- * Call ioctl, restarting if it is interrupted
+ * Call ioctl, restarting if it is interupted
*/
-drm_public int
+int
drmIoctl(int fd, unsigned long request, void *arg)
{
int ret;
@@ -201,7 +199,7 @@
return st.st_rdev;
}
-drm_public drmHashEntry *drmGetEntry(int fd)
+drmHashEntry *drmGetEntry(int fd)
{
unsigned long key = drmGetKeyFromFd(fd);
void *value;
@@ -289,7 +287,7 @@
*
* \internal
* Checks for failure. If failure was caused by signal call chown again.
- * If any other failure happened then it will output error message using
+ * If any other failure happened then it will output error mesage using
* drmMsg() call.
*/
#if !UDEV
@@ -407,7 +405,7 @@
}
#endif
- fd = open(buf, O_RDWR | O_CLOEXEC, 0);
+ fd = open(buf, O_RDWR, 0);
drmMsg("drmOpenDevice: open result is %d, (%s)\n",
fd, fd < 0 ? strerror(errno) : "OK");
if (fd >= 0)
@@ -427,7 +425,7 @@
chmod(buf, devmode);
}
}
- fd = open(buf, O_RDWR | O_CLOEXEC, 0);
+ fd = open(buf, O_RDWR, 0);
drmMsg("drmOpenDevice: open result is %d, (%s)\n",
fd, fd < 0 ? strerror(errno) : "OK");
if (fd >= 0)
@@ -476,7 +474,7 @@
};
sprintf(buf, dev_name, DRM_DIR_NAME, minor);
- if ((fd = open(buf, O_RDWR | O_CLOEXEC, 0)) >= 0)
+ if ((fd = open(buf, O_RDWR, 0)) >= 0)
return fd;
return -errno;
}
@@ -492,7 +490,7 @@
* minor and get version information. For backward compatibility with older
* Linux implementations, /proc/dri is also checked.
*/
-drm_public int drmAvailable(void)
+int drmAvailable(void)
{
drmVersionPtr version;
int retval = 0;
@@ -727,7 +725,7 @@
* It calls drmOpenByBusid() if \p busid is specified or drmOpenByName()
* otherwise.
*/
-drm_public int drmOpen(const char *name, const char *busid)
+int drmOpen(const char *name, const char *busid)
{
return drmOpenWithType(name, busid, DRM_NODE_PRIMARY);
}
@@ -748,7 +746,7 @@
* It calls drmOpenByBusid() if \p busid is specified or drmOpenByName()
* otherwise.
*/
-drm_public int drmOpenWithType(const char *name, const char *busid, int type)
+int drmOpenWithType(const char *name, const char *busid, int type)
{
if (name != NULL && drm_server_info &&
drm_server_info->load_module && !drmAvailable()) {
@@ -771,12 +769,12 @@
return -1;
}
-drm_public int drmOpenControl(int minor)
+int drmOpenControl(int minor)
{
return drmOpenMinor(minor, 0, DRM_NODE_CONTROL);
}
-drm_public int drmOpenRender(int minor)
+int drmOpenRender(int minor)
{
return drmOpenMinor(minor, 0, DRM_NODE_RENDER);
}
@@ -790,7 +788,7 @@
* It frees the memory pointed by \p %v as well as all the non-null strings
* pointers in it.
*/
-drm_public void drmFreeVersion(drmVersionPtr v)
+void drmFreeVersion(drmVersionPtr v)
{
if (!v)
return;
@@ -860,7 +858,7 @@
* first with zeros to get the string lengths, and then the actually strings.
* It also null-terminates them since they might not be already.
*/
-drm_public drmVersionPtr drmGetVersion(int fd)
+drmVersionPtr drmGetVersion(int fd)
{
drmVersionPtr retval;
drm_version_t *version = drmMalloc(sizeof(*version));
@@ -908,7 +906,7 @@
* This function allocates and fills a drm_version structure with a hard coded
* version number.
*/
-drm_public drmVersionPtr drmGetLibVersion(int fd)
+drmVersionPtr drmGetLibVersion(int fd)
{
drm_version_t *version = drmMalloc(sizeof(*version));
@@ -929,7 +927,7 @@
return (drmVersionPtr)version;
}
-drm_public int drmGetCap(int fd, uint64_t capability, uint64_t *value)
+int drmGetCap(int fd, uint64_t capability, uint64_t *value)
{
struct drm_get_cap cap;
int ret;
@@ -945,7 +943,7 @@
return 0;
}
-drm_public int drmSetClientCap(int fd, uint64_t capability, uint64_t value)
+int drmSetClientCap(int fd, uint64_t capability, uint64_t value)
{
struct drm_set_client_cap cap;
@@ -964,7 +962,7 @@
* \internal
* This function is just frees the memory pointed by \p busid.
*/
-drm_public void drmFreeBusid(const char *busid)
+void drmFreeBusid(const char *busid)
{
drmFree((void *)busid);
}
@@ -982,7 +980,7 @@
* get the string length and data, passing the arguments in a drm_unique
* structure.
*/
-drm_public char *drmGetBusid(int fd)
+char *drmGetBusid(int fd)
{
drm_unique_t u;
@@ -1013,7 +1011,7 @@
* This function is a wrapper around the DRM_IOCTL_SET_UNIQUE ioctl, passing
* the arguments in a drm_unique structure.
*/
-drm_public int drmSetBusid(int fd, const char *busid)
+int drmSetBusid(int fd, const char *busid)
{
drm_unique_t u;
@@ -1027,7 +1025,7 @@
return 0;
}
-drm_public int drmGetMagic(int fd, drm_magic_t * magic)
+int drmGetMagic(int fd, drm_magic_t * magic)
{
drm_auth_t auth;
@@ -1040,7 +1038,7 @@
return 0;
}
-drm_public int drmAuthMagic(int fd, drm_magic_t magic)
+int drmAuthMagic(int fd, drm_magic_t magic)
{
drm_auth_t auth;
@@ -1101,8 +1099,8 @@
* This function is a wrapper around the DRM_IOCTL_ADD_MAP ioctl, passing
* the arguments in a drm_map structure.
*/
-drm_public int drmAddMap(int fd, drm_handle_t offset, drmSize size, drmMapType type,
- drmMapFlags flags, drm_handle_t *handle)
+int drmAddMap(int fd, drm_handle_t offset, drmSize size, drmMapType type,
+ drmMapFlags flags, drm_handle_t *handle)
{
drm_map_t map;
@@ -1118,7 +1116,7 @@
return 0;
}
-drm_public int drmRmMap(int fd, drm_handle_t handle)
+int drmRmMap(int fd, drm_handle_t handle)
{
drm_map_t map;
@@ -1146,8 +1144,8 @@
*
* \sa drm_buf_desc.
*/
-drm_public int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags,
- int agp_offset)
+int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags,
+ int agp_offset)
{
drm_buf_desc_t request;
@@ -1162,7 +1160,7 @@
return request.count;
}
-drm_public int drmMarkBufs(int fd, double low, double high)
+int drmMarkBufs(int fd, double low, double high)
{
drm_buf_info_t info;
int i;
@@ -1213,7 +1211,7 @@
* This function is a wrapper around the DRM_IOCTL_FREE_BUFS ioctl, passing
* the arguments in a drm_buf_free structure.
*/
-drm_public int drmFreeBufs(int fd, int count, int *list)
+int drmFreeBufs(int fd, int count, int *list)
{
drm_buf_free_t request;
@@ -1234,7 +1232,7 @@
* \internal
* This function closes the file descriptor.
*/
-drm_public int drmClose(int fd)
+int drmClose(int fd)
{
unsigned long key = drmGetKeyFromFd(fd);
drmHashEntry *entry = drmGetEntry(fd);
@@ -1265,8 +1263,7 @@
* \internal
* This function is a wrapper for mmap().
*/
-drm_public int drmMap(int fd, drm_handle_t handle, drmSize size,
- drmAddressPtr address)
+int drmMap(int fd, drm_handle_t handle, drmSize size, drmAddressPtr address)
{
static unsigned long pagesize_mask = 0;
@@ -1296,12 +1293,12 @@
* \internal
* This function is a wrapper for munmap().
*/
-drm_public int drmUnmap(drmAddress address, drmSize size)
+int drmUnmap(drmAddress address, drmSize size)
{
return drm_munmap(address, size);
}
-drm_public drmBufInfoPtr drmGetBufInfo(int fd)
+drmBufInfoPtr drmGetBufInfo(int fd)
{
drm_buf_info_t info;
drmBufInfoPtr retval;
@@ -1351,7 +1348,7 @@
* information about the buffers in a drm_buf_map structure into the
* client-visible data structures.
*/
-drm_public drmBufMapPtr drmMapBufs(int fd)
+drmBufMapPtr drmMapBufs(int fd)
{
drm_buf_map_t bufs;
drmBufMapPtr retval;
@@ -1396,7 +1393,7 @@
* Calls munmap() for every buffer stored in \p bufs and frees the
* memory allocated by drmMapBufs().
*/
-drm_public int drmUnmapBufs(drmBufMapPtr bufs)
+int drmUnmapBufs(drmBufMapPtr bufs)
{
int i;
@@ -1424,7 +1421,7 @@
* Assemble the arguments into a drm_dma structure and keeps issuing the
* DRM_IOCTL_DMA ioctl until success or until maximum number of retries.
*/
-drm_public int drmDMA(int fd, drmDMAReqPtr request)
+int drmDMA(int fd, drmDMAReqPtr request)
{
drm_dma_t dma;
int ret, i = 0;
@@ -1458,7 +1455,7 @@
*
* \param fd file descriptor.
* \param context context.
- * \param flags flags that determine the state of the hardware when the function
+ * \param flags flags that determine the sate of the hardware when the function
* returns.
*
* \return always zero.
@@ -1467,7 +1464,7 @@
* This function translates the arguments into a drm_lock structure and issue
* the DRM_IOCTL_LOCK ioctl until the lock is successfully acquired.
*/
-drm_public int drmGetLock(int fd, drm_context_t context, drmLockFlags flags)
+int drmGetLock(int fd, drm_context_t context, drmLockFlags flags)
{
drm_lock_t lock;
@@ -1498,7 +1495,7 @@
* This function is a wrapper around the DRM_IOCTL_UNLOCK ioctl, passing the
* argument in a drm_lock structure.
*/
-drm_public int drmUnlock(int fd, drm_context_t context)
+int drmUnlock(int fd, drm_context_t context)
{
drm_lock_t lock;
@@ -1507,7 +1504,7 @@
return drmIoctl(fd, DRM_IOCTL_UNLOCK, &lock);
}
-drm_public drm_context_t *drmGetReservedContextList(int fd, int *count)
+drm_context_t *drmGetReservedContextList(int fd, int *count)
{
drm_ctx_res_t res;
drm_ctx_t *list;
@@ -1544,7 +1541,7 @@
return NULL;
}
-drm_public void drmFreeReservedContextList(drm_context_t *pt)
+void drmFreeReservedContextList(drm_context_t *pt)
{
drmFree(pt);
}
@@ -1567,7 +1564,7 @@
* This function is a wrapper around the DRM_IOCTL_ADD_CTX ioctl, passing the
* argument in a drm_ctx structure.
*/
-drm_public int drmCreateContext(int fd, drm_context_t *handle)
+int drmCreateContext(int fd, drm_context_t *handle)
{
drm_ctx_t ctx;
@@ -1578,7 +1575,7 @@
return 0;
}
-drm_public int drmSwitchToContext(int fd, drm_context_t context)
+int drmSwitchToContext(int fd, drm_context_t context)
{
drm_ctx_t ctx;
@@ -1589,8 +1586,7 @@
return 0;
}
-drm_public int drmSetContextFlags(int fd, drm_context_t context,
- drm_context_tFlags flags)
+int drmSetContextFlags(int fd, drm_context_t context, drm_context_tFlags flags)
{
drm_ctx_t ctx;
@@ -1611,8 +1607,8 @@
return 0;
}
-drm_public int drmGetContextFlags(int fd, drm_context_t context,
- drm_context_tFlagsPtr flags)
+int drmGetContextFlags(int fd, drm_context_t context,
+ drm_context_tFlagsPtr flags)
{
drm_ctx_t ctx;
@@ -1645,7 +1641,7 @@
* This function is a wrapper around the DRM_IOCTL_RM_CTX ioctl, passing the
* argument in a drm_ctx structure.
*/
-drm_public int drmDestroyContext(int fd, drm_context_t handle)
+int drmDestroyContext(int fd, drm_context_t handle)
{
drm_ctx_t ctx;
@@ -1656,7 +1652,7 @@
return 0;
}
-drm_public int drmCreateDrawable(int fd, drm_drawable_t *handle)
+int drmCreateDrawable(int fd, drm_drawable_t *handle)
{
drm_draw_t draw;
@@ -1667,7 +1663,7 @@
return 0;
}
-drm_public int drmDestroyDrawable(int fd, drm_drawable_t handle)
+int drmDestroyDrawable(int fd, drm_drawable_t handle)
{
drm_draw_t draw;
@@ -1678,9 +1674,9 @@
return 0;
}
-drm_public int drmUpdateDrawableInfo(int fd, drm_drawable_t handle,
- drm_drawable_info_type_t type,
- unsigned int num, void *data)
+int drmUpdateDrawableInfo(int fd, drm_drawable_t handle,
+ drm_drawable_info_type_t type, unsigned int num,
+ void *data)
{
drm_update_draw_t update;
@@ -1696,8 +1692,7 @@
return 0;
}
-drm_public int drmCrtcGetSequence(int fd, uint32_t crtcId, uint64_t *sequence,
- uint64_t *ns)
+int drmCrtcGetSequence(int fd, uint32_t crtcId, uint64_t *sequence, uint64_t *ns)
{
struct drm_crtc_get_sequence get_seq;
int ret;
@@ -1715,10 +1710,8 @@
return 0;
}
-drm_public int drmCrtcQueueSequence(int fd, uint32_t crtcId, uint32_t flags,
- uint64_t sequence,
- uint64_t *sequence_queued,
- uint64_t user_data)
+int drmCrtcQueueSequence(int fd, uint32_t crtcId, uint32_t flags, uint64_t sequence,
+ uint64_t *sequence_queued, uint64_t user_data)
{
struct drm_crtc_queue_sequence queue_seq;
int ret;
@@ -1748,7 +1741,7 @@
* \internal
* This function is a wrapper around the DRM_IOCTL_AGP_ACQUIRE ioctl.
*/
-drm_public int drmAgpAcquire(int fd)
+int drmAgpAcquire(int fd)
{
if (drmIoctl(fd, DRM_IOCTL_AGP_ACQUIRE, NULL))
return -errno;
@@ -1766,7 +1759,7 @@
* \internal
* This function is a wrapper around the DRM_IOCTL_AGP_RELEASE ioctl.
*/
-drm_public int drmAgpRelease(int fd)
+int drmAgpRelease(int fd)
{
if (drmIoctl(fd, DRM_IOCTL_AGP_RELEASE, NULL))
return -errno;
@@ -1786,7 +1779,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_ENABLE ioctl, passing the
* argument in a drm_agp_mode structure.
*/
-drm_public int drmAgpEnable(int fd, unsigned long mode)
+int drmAgpEnable(int fd, unsigned long mode)
{
drm_agp_mode_t m;
@@ -1814,8 +1807,8 @@
* This function is a wrapper around the DRM_IOCTL_AGP_ALLOC ioctl, passing the
* arguments in a drm_agp_buffer structure.
*/
-drm_public int drmAgpAlloc(int fd, unsigned long size, unsigned long type,
- unsigned long *address, drm_handle_t *handle)
+int drmAgpAlloc(int fd, unsigned long size, unsigned long type,
+ unsigned long *address, drm_handle_t *handle)
{
drm_agp_buffer_t b;
@@ -1844,7 +1837,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_FREE ioctl, passing the
* argument in a drm_agp_buffer structure.
*/
-drm_public int drmAgpFree(int fd, drm_handle_t handle)
+int drmAgpFree(int fd, drm_handle_t handle)
{
drm_agp_buffer_t b;
@@ -1869,7 +1862,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_BIND ioctl, passing the
* argument in a drm_agp_binding structure.
*/
-drm_public int drmAgpBind(int fd, drm_handle_t handle, unsigned long offset)
+int drmAgpBind(int fd, drm_handle_t handle, unsigned long offset)
{
drm_agp_binding_t b;
@@ -1894,7 +1887,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_UNBIND ioctl, passing
* the argument in a drm_agp_binding structure.
*/
-drm_public int drmAgpUnbind(int fd, drm_handle_t handle)
+int drmAgpUnbind(int fd, drm_handle_t handle)
{
drm_agp_binding_t b;
@@ -1917,7 +1910,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public int drmAgpVersionMajor(int fd)
+int drmAgpVersionMajor(int fd)
{
drm_agp_info_t i;
@@ -1940,7 +1933,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public int drmAgpVersionMinor(int fd)
+int drmAgpVersionMinor(int fd)
{
drm_agp_info_t i;
@@ -1963,7 +1956,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned long drmAgpGetMode(int fd)
+unsigned long drmAgpGetMode(int fd)
{
drm_agp_info_t i;
@@ -1986,7 +1979,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned long drmAgpBase(int fd)
+unsigned long drmAgpBase(int fd)
{
drm_agp_info_t i;
@@ -2009,7 +2002,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned long drmAgpSize(int fd)
+unsigned long drmAgpSize(int fd)
{
drm_agp_info_t i;
@@ -2032,7 +2025,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned long drmAgpMemoryUsed(int fd)
+unsigned long drmAgpMemoryUsed(int fd)
{
drm_agp_info_t i;
@@ -2055,7 +2048,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned long drmAgpMemoryAvail(int fd)
+unsigned long drmAgpMemoryAvail(int fd)
{
drm_agp_info_t i;
@@ -2078,7 +2071,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned int drmAgpVendorId(int fd)
+unsigned int drmAgpVendorId(int fd)
{
drm_agp_info_t i;
@@ -2101,7 +2094,7 @@
* This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the
* necessary information in a drm_agp_info structure.
*/
-drm_public unsigned int drmAgpDeviceId(int fd)
+unsigned int drmAgpDeviceId(int fd)
{
drm_agp_info_t i;
@@ -2112,8 +2105,7 @@
return i.id_device;
}
-drm_public int drmScatterGatherAlloc(int fd, unsigned long size,
- drm_handle_t *handle)
+int drmScatterGatherAlloc(int fd, unsigned long size, drm_handle_t *handle)
{
drm_scatter_gather_t sg;
@@ -2127,7 +2119,7 @@
return 0;
}
-drm_public int drmScatterGatherFree(int fd, drm_handle_t handle)
+int drmScatterGatherFree(int fd, drm_handle_t handle)
{
drm_scatter_gather_t sg;
@@ -2149,7 +2141,7 @@
* \internal
* This function is a wrapper around the DRM_IOCTL_WAIT_VBLANK ioctl.
*/
-drm_public int drmWaitVBlank(int fd, drmVBlankPtr vbl)
+int drmWaitVBlank(int fd, drmVBlankPtr vbl)
{
struct timespec timeout, cur;
int ret;
@@ -2181,7 +2173,7 @@
return ret;
}
-drm_public int drmError(int err, const char *label)
+int drmError(int err, const char *label)
{
switch (err) {
case DRM_ERR_NO_DEVICE:
@@ -2218,7 +2210,7 @@
* This function is a wrapper around the DRM_IOCTL_CONTROL ioctl, passing the
* argument in a drm_control structure.
*/
-drm_public int drmCtlInstHandler(int fd, int irq)
+int drmCtlInstHandler(int fd, int irq)
{
drm_control_t ctl;
@@ -2242,7 +2234,7 @@
* This function is a wrapper around the DRM_IOCTL_CONTROL ioctl, passing the
* argument in a drm_control structure.
*/
-drm_public int drmCtlUninstHandler(int fd)
+int drmCtlUninstHandler(int fd)
{
drm_control_t ctl;
@@ -2254,7 +2246,7 @@
return 0;
}
-drm_public int drmFinish(int fd, int context, drmLockFlags flags)
+int drmFinish(int fd, int context, drmLockFlags flags)
{
drm_lock_t lock;
@@ -2285,8 +2277,7 @@
* This function is a wrapper around the DRM_IOCTL_IRQ_BUSID ioctl, passing the
* arguments in a drm_irq_busid structure.
*/
-drm_public int drmGetInterruptFromBusID(int fd, int busnum, int devnum,
- int funcnum)
+int drmGetInterruptFromBusID(int fd, int busnum, int devnum, int funcnum)
{
drm_irq_busid_t p;
@@ -2299,7 +2290,7 @@
return p.irq;
}
-drm_public int drmAddContextTag(int fd, drm_context_t context, void *tag)
+int drmAddContextTag(int fd, drm_context_t context, void *tag)
{
drmHashEntry *entry = drmGetEntry(fd);
@@ -2310,14 +2301,14 @@
return 0;
}
-drm_public int drmDelContextTag(int fd, drm_context_t context)
+int drmDelContextTag(int fd, drm_context_t context)
{
drmHashEntry *entry = drmGetEntry(fd);
return drmHashDelete(entry->tagTable, context);
}
-drm_public void *drmGetContextTag(int fd, drm_context_t context)
+void *drmGetContextTag(int fd, drm_context_t context)
{
drmHashEntry *entry = drmGetEntry(fd);
void *value;
@@ -2328,8 +2319,8 @@
return value;
}
-drm_public int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id,
- drm_handle_t handle)
+int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id,
+ drm_handle_t handle)
{
drm_ctx_priv_map_t map;
@@ -2342,8 +2333,8 @@
return 0;
}
-drm_public int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id,
- drm_handle_t *handle)
+int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id,
+ drm_handle_t *handle)
{
drm_ctx_priv_map_t map;
@@ -2358,9 +2349,9 @@
return 0;
}
-drm_public int drmGetMap(int fd, int idx, drm_handle_t *offset, drmSize *size,
- drmMapType *type, drmMapFlags *flags,
- drm_handle_t *handle, int *mtrr)
+int drmGetMap(int fd, int idx, drm_handle_t *offset, drmSize *size,
+ drmMapType *type, drmMapFlags *flags, drm_handle_t *handle,
+ int *mtrr)
{
drm_map_t map;
@@ -2377,8 +2368,8 @@
return 0;
}
-drm_public int drmGetClient(int fd, int idx, int *auth, int *pid, int *uid,
- unsigned long *magic, unsigned long *iocs)
+int drmGetClient(int fd, int idx, int *auth, int *pid, int *uid,
+ unsigned long *magic, unsigned long *iocs)
{
drm_client_t client;
@@ -2394,7 +2385,7 @@
return 0;
}
-drm_public int drmGetStats(int fd, drmStatsT *stats)
+int drmGetStats(int fd, drmStatsT *stats)
{
drm_stats_t s;
unsigned i;
@@ -2532,7 +2523,7 @@
* It issues a read-write ioctl given by
* \code DRM_COMMAND_BASE + drmCommandIndex \endcode.
*/
-drm_public int drmSetInterfaceVersion(int fd, drmSetVersion *version)
+int drmSetInterfaceVersion(int fd, drmSetVersion *version)
{
int retcode = 0;
drm_set_version_t sv;
@@ -2567,7 +2558,7 @@
* It issues a ioctl given by
* \code DRM_COMMAND_BASE + drmCommandIndex \endcode.
*/
-drm_public int drmCommandNone(int fd, unsigned long drmCommandIndex)
+int drmCommandNone(int fd, unsigned long drmCommandIndex)
{
unsigned long request;
@@ -2594,8 +2585,8 @@
* It issues a read ioctl given by
* \code DRM_COMMAND_BASE + drmCommandIndex \endcode.
*/
-drm_public int drmCommandRead(int fd, unsigned long drmCommandIndex,
- void *data, unsigned long size)
+int drmCommandRead(int fd, unsigned long drmCommandIndex, void *data,
+ unsigned long size)
{
unsigned long request;
@@ -2623,8 +2614,8 @@
* It issues a write ioctl given by
* \code DRM_COMMAND_BASE + drmCommandIndex \endcode.
*/
-drm_public int drmCommandWrite(int fd, unsigned long drmCommandIndex,
- void *data, unsigned long size)
+int drmCommandWrite(int fd, unsigned long drmCommandIndex, void *data,
+ unsigned long size)
{
unsigned long request;
@@ -2652,8 +2643,8 @@
* It issues a read-write ioctl given by
* \code DRM_COMMAND_BASE + drmCommandIndex \endcode.
*/
-drm_public int drmCommandWriteRead(int fd, unsigned long drmCommandIndex,
- void *data, unsigned long size)
+int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, void *data,
+ unsigned long size)
{
unsigned long request;
@@ -2675,13 +2666,14 @@
static int nr_fds = 0;
-drm_public int drmOpenOnce(void *unused, const char *BusID, int *newlyopened)
+int drmOpenOnce(void *unused,
+ const char *BusID,
+ int *newlyopened)
{
return drmOpenOnceWithType(BusID, newlyopened, DRM_NODE_PRIMARY);
}
-drm_public int drmOpenOnceWithType(const char *BusID, int *newlyopened,
- int type)
+int drmOpenOnceWithType(const char *BusID, int *newlyopened, int type)
{
int i;
int fd;
@@ -2714,7 +2706,7 @@
return fd;
}
-drm_public void drmCloseOnce(int fd)
+void drmCloseOnce(int fd)
{
int i;
@@ -2733,35 +2725,17 @@
}
}
-drm_public int drmSetMaster(int fd)
+int drmSetMaster(int fd)
{
return drmIoctl(fd, DRM_IOCTL_SET_MASTER, NULL);
}
-drm_public int drmDropMaster(int fd)
+int drmDropMaster(int fd)
{
return drmIoctl(fd, DRM_IOCTL_DROP_MASTER, NULL);
}
-drm_public int drmIsMaster(int fd)
-{
- /* Detect master by attempting something that requires master.
- *
- * Authenticating magic tokens requires master and 0 is an
- * internal kernel detail which we could use. Attempting this on
- * a master fd would fail therefore fail with EINVAL because 0
- * is invalid.
- *
- * A non-master fd will fail with EACCES, as the kernel checks
- * for master before attempting to do anything else.
- *
- * Since we don't want to leak implementation details, use
- * EACCES.
- */
- return drmAuthMagic(fd, 0) != -EACCES;
-}
-
-drm_public char *drmGetDeviceNameFromFd(int fd)
+char *drmGetDeviceNameFromFd(int fd)
{
char name[128];
struct stat sbuf;
@@ -2787,21 +2761,7 @@
return strdup(name);
}
-static bool drmNodeIsDRM(int maj, int min)
-{
-#ifdef __linux__
- char path[64];
- struct stat sbuf;
-
- snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm",
- maj, min);
- return stat(path, &sbuf) == 0;
-#else
- return maj == DRM_MAJOR;
-#endif
-}
-
-drm_public int drmGetNodeTypeFromFd(int fd)
+int drmGetNodeTypeFromFd(int fd)
{
struct stat sbuf;
int maj, min, type;
@@ -2812,7 +2772,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode)) {
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode)) {
errno = EINVAL;
return -1;
}
@@ -2823,8 +2783,7 @@
return type;
}
-drm_public int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags,
- int *prime_fd)
+int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd)
{
struct drm_prime_handle args;
int ret;
@@ -2841,7 +2800,7 @@
return 0;
}
-drm_public int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle)
+int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle)
{
struct drm_prime_handle args;
int ret;
@@ -2878,7 +2837,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return NULL;
snprintf(buf, sizeof(buf), "/sys/dev/char/%d:%d/device/drm", maj, min);
@@ -2896,8 +2855,6 @@
return strdup(dev_name);
}
}
-
- closedir(sysdir);
return NULL;
#else
struct stat sbuf;
@@ -2912,7 +2869,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return NULL;
switch (type) {
@@ -2941,12 +2898,12 @@
#endif
}
-drm_public char *drmGetPrimaryDeviceNameFromFd(int fd)
+char *drmGetPrimaryDeviceNameFromFd(int fd)
{
return drmGetMinorNameForFD(fd, DRM_NODE_PRIMARY);
}
-drm_public char *drmGetRenderDeviceNameFromFd(int fd)
+char *drmGetRenderDeviceNameFromFd(int fd)
{
return drmGetMinorNameForFD(fd, DRM_NODE_RENDER);
}
@@ -2995,26 +2952,12 @@
}
#endif
-/* Little white lie to avoid major rework of the existing code */
-#define DRM_BUS_VIRTIO 0x10
-
static int drmParseSubsystemType(int maj, int min)
{
#ifdef __linux__
char path[PATH_MAX + 1];
char link[PATH_MAX + 1] = "";
char *name;
- struct {
- const char *name;
- int bus_type;
- } bus_types[] = {
- { "/pci", DRM_BUS_PCI },
- { "/usb", DRM_BUS_USB },
- { "/platform", DRM_BUS_PLATFORM },
- { "/spi", DRM_BUS_PLATFORM },
- { "/host1x", DRM_BUS_HOST1X },
- { "/virtio", DRM_BUS_VIRTIO },
- };
snprintf(path, PATH_MAX, "/sys/dev/char/%d:%d/device/subsystem",
maj, min);
@@ -3026,13 +2969,20 @@
if (!name)
return -EINVAL;
- for (unsigned i = 0; i < ARRAY_SIZE(bus_types); i++) {
- if (strncmp(name, bus_types[i].name, strlen(bus_types[i].name)) == 0)
- return bus_types[i].bus_type;
- }
+ if (strncmp(name, "/pci", 4) == 0)
+ return DRM_BUS_PCI;
+
+ if (strncmp(name, "/usb", 4) == 0)
+ return DRM_BUS_USB;
+
+ if (strncmp(name, "/platform", 9) == 0)
+ return DRM_BUS_PLATFORM;
+
+ if (strncmp(name, "/host1x", 7) == 0)
+ return DRM_BUS_HOST1X;
return -EINVAL;
-#elif defined(__OpenBSD__) || defined(__DragonFly__)
+#elif defined(__OpenBSD__)
return DRM_BUS_PCI;
#else
#warning "Missing implementation of drmParseSubsystemType"
@@ -3040,32 +2990,16 @@
#endif
}
-static void
-get_pci_path(int maj, int min, char *pci_path)
-{
- char path[PATH_MAX + 1], *term;
-
- snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
- if (!realpath(path, pci_path)) {
- strcpy(pci_path, path);
- return;
- }
-
- term = strrchr(pci_path, '/');
- if (term && strncmp(term, "/virtio", 7) == 0)
- *term = 0;
-}
-
static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info)
{
#ifdef __linux__
unsigned int domain, bus, dev, func;
- char pci_path[PATH_MAX + 1], *value;
+ char path[PATH_MAX + 1], *value;
int num;
- get_pci_path(maj, min, pci_path);
+ snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
- value = sysfs_uevent_get(pci_path, "PCI_SLOT_NAME");
+ value = sysfs_uevent_get(path, "PCI_SLOT_NAME");
if (!value)
return -ENOENT;
@@ -3081,7 +3015,7 @@
info->func = func;
return 0;
-#elif defined(__OpenBSD__) || defined(__DragonFly__)
+#elif defined(__OpenBSD__)
struct drm_pciinfo pinfo;
int fd, type;
@@ -3111,7 +3045,7 @@
#endif
}
-drm_public int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b)
+int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b)
{
if (a == NULL || b == NULL)
return 0;
@@ -3170,6 +3104,7 @@
drmPciDeviceInfoPtr device,
bool ignore_revision)
{
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static const char *attrs[] = {
"revision", /* Older kernels are missing the file, so check for it first */
"vendor",
@@ -3177,15 +3112,14 @@
"subsystem_vendor",
"subsystem_device",
};
- char path[PATH_MAX + 1], pci_path[PATH_MAX + 1];
+ char path[PATH_MAX + 1];
unsigned int data[ARRAY_SIZE(attrs)];
FILE *fp;
int ret;
- get_pci_path(maj, min, pci_path);
-
for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
- snprintf(path, PATH_MAX, "%s/%s", pci_path, attrs[i]);
+ snprintf(path, PATH_MAX, "/sys/dev/char/%d:%d/device/%s", maj, min,
+ attrs[i]);
fp = fopen(path, "r");
if (!fp)
return -errno;
@@ -3209,13 +3143,11 @@
static int parse_config_sysfs_file(int maj, int min,
drmPciDeviceInfoPtr device)
{
- char path[PATH_MAX + 1], pci_path[PATH_MAX + 1];
+ char path[PATH_MAX + 1];
unsigned char config[64];
int fd, ret;
- get_pci_path(maj, min, pci_path);
-
- snprintf(path, PATH_MAX, "%s/config", pci_path);
+ snprintf(path, PATH_MAX, "/sys/dev/char/%d:%d/device/config", maj, min);
fd = open(path, O_RDONLY);
if (fd < 0)
return -errno;
@@ -3247,7 +3179,7 @@
return parse_config_sysfs_file(maj, min, device);
return 0;
-#elif defined(__OpenBSD__) || defined(__DragonFly__)
+#elif defined(__OpenBSD__)
struct drm_pciinfo pinfo;
int fd, type;
@@ -3310,7 +3242,7 @@
}
}
-drm_public void drmFreeDevice(drmDevicePtr *device)
+void drmFreeDevice(drmDevicePtr *device)
{
if (device == NULL)
return;
@@ -3331,7 +3263,7 @@
*device = NULL;
}
-drm_public void drmFreeDevices(drmDevicePtr devices[], int count)
+void drmFreeDevices(drmDevicePtr devices[], int count)
{
int i;
@@ -3528,97 +3460,69 @@
return ret;
}
-static int drmParseOFBusInfo(int maj, int min, char *fullname)
+static int drmParsePlatformBusInfo(int maj, int min, drmPlatformBusInfoPtr info)
{
#ifdef __linux__
- char path[PATH_MAX + 1], *name, *tmp_name;
+ char path[PATH_MAX + 1], *name;
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
name = sysfs_uevent_get(path, "OF_FULLNAME");
- tmp_name = name;
- if (!name) {
- /* If the device lacks OF data, pick the MODALIAS info */
- name = sysfs_uevent_get(path, "MODALIAS");
- if (!name)
- return -ENOENT;
+ if (!name)
+ return -ENOENT;
- /* .. and strip the MODALIAS=[platform,usb...]: part. */
- tmp_name = strrchr(name, ':');
- if (!tmp_name) {
- free(name);
- return -ENOENT;
- }
- tmp_name++;
- }
-
- strncpy(fullname, tmp_name, DRM_PLATFORM_DEVICE_NAME_LEN);
- fullname[DRM_PLATFORM_DEVICE_NAME_LEN - 1] = '\0';
+ strncpy(info->fullname, name, DRM_PLATFORM_DEVICE_NAME_LEN);
+ info->fullname[DRM_PLATFORM_DEVICE_NAME_LEN - 1] = '\0';
free(name);
return 0;
#else
-#warning "Missing implementation of drmParseOFBusInfo"
+#warning "Missing implementation of drmParsePlatformBusInfo"
return -EINVAL;
#endif
}
-static int drmParseOFDeviceInfo(int maj, int min, char ***compatible)
+static int drmParsePlatformDeviceInfo(int maj, int min,
+ drmPlatformDeviceInfoPtr info)
{
#ifdef __linux__
- char path[PATH_MAX + 1], *value, *tmp_name;
+ char path[PATH_MAX + 1], *value;
unsigned int count, i;
int err;
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
value = sysfs_uevent_get(path, "OF_COMPATIBLE_N");
- if (value) {
- sscanf(value, "%u", &count);
- free(value);
- } else {
- /* Assume one entry if the device lack OF data */
- count = 1;
- }
+ if (!value)
+ return -ENOENT;
- *compatible = calloc(count + 1, sizeof(char *));
- if (!*compatible)
+ sscanf(value, "%u", &count);
+ free(value);
+
+ info->compatible = calloc(count + 1, sizeof(*info->compatible));
+ if (!info->compatible)
return -ENOMEM;
for (i = 0; i < count; i++) {
value = sysfs_uevent_get(path, "OF_COMPATIBLE_%u", i);
- tmp_name = value;
if (!value) {
- /* If the device lacks OF data, pick the MODALIAS info */
- value = sysfs_uevent_get(path, "MODALIAS");
- if (!value) {
- err = -ENOENT;
- goto free;
- }
-
- /* .. and strip the MODALIAS=[platform,usb...]: part. */
- tmp_name = strrchr(value, ':');
- if (!tmp_name) {
- free(value);
- return -ENOENT;
- }
- tmp_name = strdup(tmp_name + 1);
- free(value);
+ err = -ENOENT;
+ goto free;
}
- (*compatible)[i] = tmp_name;
+ info->compatible[i] = value;
}
return 0;
free:
while (i--)
- free((*compatible)[i]);
+ free(info->compatible[i]);
- free(*compatible);
+ free(info->compatible);
return err;
#else
-#warning "Missing implementation of drmParseOFDeviceInfo"
+#warning "Missing implementation of drmParsePlatformDeviceInfo"
return -EINVAL;
#endif
}
@@ -3641,7 +3545,7 @@
dev->businfo.platform = (drmPlatformBusInfoPtr)ptr;
- ret = drmParseOFBusInfo(maj, min, dev->businfo.platform->fullname);
+ ret = drmParsePlatformBusInfo(maj, min, dev->businfo.platform);
if (ret < 0)
goto free_device;
@@ -3649,7 +3553,7 @@
ptr += sizeof(drmPlatformBusInfo);
dev->deviceinfo.platform = (drmPlatformDeviceInfoPtr)ptr;
- ret = drmParseOFDeviceInfo(maj, min, &dev->deviceinfo.platform->compatible);
+ ret = drmParsePlatformDeviceInfo(maj, min, dev->deviceinfo.platform);
if (ret < 0)
goto free_device;
}
@@ -3663,6 +3567,73 @@
return ret;
}
+static int drmParseHost1xBusInfo(int maj, int min, drmHost1xBusInfoPtr info)
+{
+#ifdef __linux__
+ char path[PATH_MAX + 1], *name;
+
+ snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
+
+ name = sysfs_uevent_get(path, "OF_FULLNAME");
+ if (!name)
+ return -ENOENT;
+
+ strncpy(info->fullname, name, DRM_HOST1X_DEVICE_NAME_LEN);
+ info->fullname[DRM_HOST1X_DEVICE_NAME_LEN - 1] = '\0';
+ free(name);
+
+ return 0;
+#else
+#warning "Missing implementation of drmParseHost1xBusInfo"
+ return -EINVAL;
+#endif
+}
+
+static int drmParseHost1xDeviceInfo(int maj, int min,
+ drmHost1xDeviceInfoPtr info)
+{
+#ifdef __linux__
+ char path[PATH_MAX + 1], *value;
+ unsigned int count, i;
+ int err;
+
+ snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min);
+
+ value = sysfs_uevent_get(path, "OF_COMPATIBLE_N");
+ if (!value)
+ return -ENOENT;
+
+ sscanf(value, "%u", &count);
+ free(value);
+
+ info->compatible = calloc(count + 1, sizeof(*info->compatible));
+ if (!info->compatible)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ value = sysfs_uevent_get(path, "OF_COMPATIBLE_%u", i);
+ if (!value) {
+ err = -ENOENT;
+ goto free;
+ }
+
+ info->compatible[i] = value;
+ }
+
+ return 0;
+
+free:
+ while (i--)
+ free(info->compatible[i]);
+
+ free(info->compatible);
+ return err;
+#else
+#warning "Missing implementation of drmParseHost1xDeviceInfo"
+ return -EINVAL;
+#endif
+}
+
static int drmProcessHost1xDevice(drmDevicePtr *device,
const char *node, int node_type,
int maj, int min, bool fetch_deviceinfo,
@@ -3681,7 +3652,7 @@
dev->businfo.host1x = (drmHost1xBusInfoPtr)ptr;
- ret = drmParseOFBusInfo(maj, min, dev->businfo.host1x->fullname);
+ ret = drmParseHost1xBusInfo(maj, min, dev->businfo.host1x);
if (ret < 0)
goto free_device;
@@ -3689,7 +3660,7 @@
ptr += sizeof(drmHost1xBusInfo);
dev->deviceinfo.host1x = (drmHost1xDeviceInfoPtr)ptr;
- ret = drmParseOFDeviceInfo(maj, min, &dev->deviceinfo.host1x->compatible);
+ ret = drmParseHost1xDeviceInfo(maj, min, dev->deviceinfo.host1x);
if (ret < 0)
goto free_device;
}
@@ -3703,53 +3674,6 @@
return ret;
}
-static int
-process_device(drmDevicePtr *device, const char *d_name,
- int req_subsystem_type,
- bool fetch_deviceinfo, uint32_t flags)
-{
- struct stat sbuf;
- char node[PATH_MAX + 1];
- int node_type, subsystem_type;
- unsigned int maj, min;
-
- node_type = drmGetNodeType(d_name);
- if (node_type < 0)
- return -1;
-
- snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name);
- if (stat(node, &sbuf))
- return -1;
-
- maj = major(sbuf.st_rdev);
- min = minor(sbuf.st_rdev);
-
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
- return -1;
-
- subsystem_type = drmParseSubsystemType(maj, min);
- if (req_subsystem_type != -1 && req_subsystem_type != subsystem_type)
- return -1;
-
- switch (subsystem_type) {
- case DRM_BUS_PCI:
- case DRM_BUS_VIRTIO:
- return drmProcessPciDevice(device, node, node_type, maj, min,
- fetch_deviceinfo, flags);
- case DRM_BUS_USB:
- return drmProcessUsbDevice(device, node, node_type, maj, min,
- fetch_deviceinfo, flags);
- case DRM_BUS_PLATFORM:
- return drmProcessPlatformDevice(device, node, node_type, maj, min,
- fetch_deviceinfo, flags);
- case DRM_BUS_HOST1X:
- return drmProcessHost1xDevice(device, node, node_type, maj, min,
- fetch_deviceinfo, flags);
- default:
- return -1;
- }
-}
-
/* Consider devices located on the same bus as duplicate and fold the respective
* entries into a single one.
*
@@ -3779,28 +3703,6 @@
return (flags & ~DRM_DEVICE_GET_PCI_REVISION);
}
-static bool
-drm_device_has_rdev(drmDevicePtr device, dev_t find_rdev)
-{
- struct stat sbuf;
-
- for (int i = 0; i < DRM_NODE_MAX; i++) {
- if (device->available_nodes & 1 << i) {
- if (stat(device->nodes[i], &sbuf) == 0 &&
- sbuf.st_rdev == find_rdev)
- return true;
- }
- }
- return false;
-}
-
-/*
- * The kernel drm core has a number of places that assume maximum of
- * 3x64 devices nodes. That's 64 for each of primary, control and
- * render nodes. Rounded it up to 256 for simplicity.
- */
-#define MAX_DRM_NODES 256
-
/**
* Get information about the opened drm device
*
@@ -3814,7 +3716,7 @@
* \note Unlike drmGetDevice it does not retrieve the pci device revision field
* unless the DRM_DEVICE_GET_PCI_REVISION \p flag is set.
*/
-drm_public int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device)
+int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device)
{
#ifdef __OpenBSD__
/*
@@ -3838,7 +3740,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return -EINVAL;
node_type = drmGetMinorType(min);
@@ -3881,14 +3783,16 @@
return 0;
#else
- drmDevicePtr local_devices[MAX_DRM_NODES];
+ drmDevicePtr *local_devices;
drmDevicePtr d;
DIR *sysdir;
struct dirent *dent;
struct stat sbuf;
- int subsystem_type;
+ char node[PATH_MAX + 1];
+ int node_type, subsystem_type;
int maj, min;
int ret, i, node_count;
+ int max_count = 16;
dev_t find_rdev;
if (drm_device_validate_flags(flags))
@@ -3904,52 +3808,112 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return -EINVAL;
subsystem_type = drmParseSubsystemType(maj, min);
- if (subsystem_type < 0)
- return subsystem_type;
+
+ local_devices = calloc(max_count, sizeof(drmDevicePtr));
+ if (local_devices == NULL)
+ return -ENOMEM;
sysdir = opendir(DRM_DIR_NAME);
- if (!sysdir)
- return -errno;
+ if (!sysdir) {
+ ret = -errno;
+ goto free_locals;
+ }
i = 0;
while ((dent = readdir(sysdir))) {
- ret = process_device(&d, dent->d_name, subsystem_type, true, flags);
- if (ret)
+ node_type = drmGetNodeType(dent->d_name);
+ if (node_type < 0)
continue;
- if (i >= MAX_DRM_NODES) {
- fprintf(stderr, "More than %d drm nodes detected. "
- "Please report a bug - that should not happen.\n"
- "Skipping extra nodes\n", MAX_DRM_NODES);
+ snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, dent->d_name);
+ if (stat(node, &sbuf))
+ continue;
+
+ maj = major(sbuf.st_rdev);
+ min = minor(sbuf.st_rdev);
+
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
+ continue;
+
+ if (drmParseSubsystemType(maj, min) != subsystem_type)
+ continue;
+
+ switch (subsystem_type) {
+ case DRM_BUS_PCI:
+ ret = drmProcessPciDevice(&d, node, node_type, maj, min, true, flags);
+ if (ret)
+ continue;
+
break;
+
+ case DRM_BUS_USB:
+ ret = drmProcessUsbDevice(&d, node, node_type, maj, min, true, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ case DRM_BUS_PLATFORM:
+ ret = drmProcessPlatformDevice(&d, node, node_type, maj, min, true, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ case DRM_BUS_HOST1X:
+ ret = drmProcessHost1xDevice(&d, node, node_type, maj, min, true, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ default:
+ continue;
}
- local_devices[i] = d;
+
+ if (i >= max_count) {
+ drmDevicePtr *temp;
+
+ max_count += 16;
+ temp = realloc(local_devices, max_count * sizeof(drmDevicePtr));
+ if (!temp)
+ goto free_devices;
+ local_devices = temp;
+ }
+
+ /* store target at local_devices[0] for ease to use below */
+ if (find_rdev == sbuf.st_rdev && i) {
+ local_devices[i] = local_devices[0];
+ local_devices[0] = d;
+ }
+ else
+ local_devices[i] = d;
i++;
}
node_count = i;
drmFoldDuplicatedDevices(local_devices, node_count);
- *device = NULL;
-
- for (i = 0; i < node_count; i++) {
- if (!local_devices[i])
- continue;
-
- if (drm_device_has_rdev(local_devices[i], find_rdev))
- *device = local_devices[i];
- else
- drmFreeDevice(&local_devices[i]);
- }
+ *device = local_devices[0];
+ drmFreeDevices(&local_devices[1], node_count - 1);
closedir(sysdir);
+ free(local_devices);
if (*device == NULL)
return -ENODEV;
return 0;
+
+free_devices:
+ drmFreeDevices(local_devices, i);
+ closedir(sysdir);
+
+free_locals:
+ free(local_devices);
+ return ret;
#endif
}
@@ -3962,7 +3926,7 @@
*
* \return zero on success, negative error code otherwise.
*/
-drm_public int drmGetDevice(int fd, drmDevicePtr *device)
+int drmGetDevice(int fd, drmDevicePtr *device)
{
return drmGetDevice2(fd, DRM_DEVICE_GET_PCI_REVISION, device);
}
@@ -3983,34 +3947,100 @@
* \note Unlike drmGetDevices it does not retrieve the pci device revision field
* unless the DRM_DEVICE_GET_PCI_REVISION \p flag is set.
*/
-drm_public int drmGetDevices2(uint32_t flags, drmDevicePtr devices[],
- int max_devices)
+int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices)
{
- drmDevicePtr local_devices[MAX_DRM_NODES];
+ drmDevicePtr *local_devices;
drmDevicePtr device;
DIR *sysdir;
struct dirent *dent;
+ struct stat sbuf;
+ char node[PATH_MAX + 1];
+ int node_type, subsystem_type;
+ int maj, min;
int ret, i, node_count, device_count;
+ int max_count = 16;
if (drm_device_validate_flags(flags))
return -EINVAL;
+ local_devices = calloc(max_count, sizeof(drmDevicePtr));
+ if (local_devices == NULL)
+ return -ENOMEM;
+
sysdir = opendir(DRM_DIR_NAME);
- if (!sysdir)
- return -errno;
+ if (!sysdir) {
+ ret = -errno;
+ goto free_locals;
+ }
i = 0;
while ((dent = readdir(sysdir))) {
- ret = process_device(&device, dent->d_name, -1, devices != NULL, flags);
- if (ret)
+ node_type = drmGetNodeType(dent->d_name);
+ if (node_type < 0)
continue;
- if (i >= MAX_DRM_NODES) {
- fprintf(stderr, "More than %d drm nodes detected. "
- "Please report a bug - that should not happen.\n"
- "Skipping extra nodes\n", MAX_DRM_NODES);
+ snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, dent->d_name);
+ if (stat(node, &sbuf))
+ continue;
+
+ maj = major(sbuf.st_rdev);
+ min = minor(sbuf.st_rdev);
+
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
+ continue;
+
+ subsystem_type = drmParseSubsystemType(maj, min);
+
+ if (subsystem_type < 0)
+ continue;
+
+ switch (subsystem_type) {
+ case DRM_BUS_PCI:
+ ret = drmProcessPciDevice(&device, node, node_type,
+ maj, min, devices != NULL, flags);
+ if (ret)
+ continue;
+
break;
+
+ case DRM_BUS_USB:
+ ret = drmProcessUsbDevice(&device, node, node_type, maj, min,
+ devices != NULL, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ case DRM_BUS_PLATFORM:
+ ret = drmProcessPlatformDevice(&device, node, node_type, maj, min,
+ devices != NULL, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ case DRM_BUS_HOST1X:
+ ret = drmProcessHost1xDevice(&device, node, node_type, maj, min,
+ devices != NULL, flags);
+ if (ret)
+ continue;
+
+ break;
+
+ default:
+ continue;
}
+
+ if (i >= max_count) {
+ drmDevicePtr *temp;
+
+ max_count += 16;
+ temp = realloc(local_devices, max_count * sizeof(drmDevicePtr));
+ if (!temp)
+ goto free_devices;
+ local_devices = temp;
+ }
+
local_devices[i] = device;
i++;
}
@@ -4032,7 +4062,16 @@
}
closedir(sysdir);
+ free(local_devices);
return device_count;
+
+free_devices:
+ drmFreeDevices(local_devices, i);
+ closedir(sysdir);
+
+free_locals:
+ free(local_devices);
+ return ret;
}
/**
@@ -4047,12 +4086,12 @@
* alternatively the number of devices stored in devices[], which is
* capped by the max_devices.
*/
-drm_public int drmGetDevices(drmDevicePtr devices[], int max_devices)
+int drmGetDevices(drmDevicePtr devices[], int max_devices)
{
return drmGetDevices2(DRM_DEVICE_GET_PCI_REVISION, devices, max_devices);
}
-drm_public char *drmGetDeviceNameFromFd2(int fd)
+char *drmGetDeviceNameFromFd2(int fd)
{
#ifdef __linux__
struct stat sbuf;
@@ -4065,7 +4104,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return NULL;
snprintf(path, sizeof(path), "/sys/dev/char/%d:%d", maj, min);
@@ -4091,7 +4130,7 @@
maj = major(sbuf.st_rdev);
min = minor(sbuf.st_rdev);
- if (!drmNodeIsDRM(maj, min) || !S_ISCHR(sbuf.st_mode))
+ if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode))
return NULL;
node_type = drmGetMinorType(min);
@@ -4124,7 +4163,7 @@
#endif
}
-drm_public int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle)
+int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle)
{
struct drm_syncobj_create args;
int ret;
@@ -4139,7 +4178,7 @@
return 0;
}
-drm_public int drmSyncobjDestroy(int fd, uint32_t handle)
+int drmSyncobjDestroy(int fd, uint32_t handle)
{
struct drm_syncobj_destroy args;
@@ -4148,7 +4187,7 @@
return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_DESTROY, &args);
}
-drm_public int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd)
+int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd)
{
struct drm_syncobj_handle args;
int ret;
@@ -4163,7 +4202,7 @@
return 0;
}
-drm_public int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle)
+int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle)
{
struct drm_syncobj_handle args;
int ret;
@@ -4178,8 +4217,7 @@
return 0;
}
-drm_public int drmSyncobjImportSyncFile(int fd, uint32_t handle,
- int sync_file_fd)
+int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd)
{
struct drm_syncobj_handle args;
@@ -4190,8 +4228,7 @@
return drmIoctl(fd, DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, &args);
}
-drm_public int drmSyncobjExportSyncFile(int fd, uint32_t handle,
- int *sync_file_fd)
+int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd)
{
struct drm_syncobj_handle args;
int ret;
@@ -4207,9 +4244,9 @@
return 0;
}
-drm_public int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled)
+int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
{
struct drm_syncobj_wait args;
int ret;
@@ -4229,8 +4266,7 @@
return ret;
}
-drm_public int drmSyncobjReset(int fd, const uint32_t *handles,
- uint32_t handle_count)
+int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count)
{
struct drm_syncobj_array args;
int ret;
@@ -4243,8 +4279,7 @@
return ret;
}
-drm_public int drmSyncobjSignal(int fd, const uint32_t *handles,
- uint32_t handle_count)
+int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count)
{
struct drm_syncobj_array args;
int ret;
@@ -4256,80 +4291,3 @@
ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_SIGNAL, &args);
return ret;
}
-
-drm_public int drmSyncobjTimelineSignal(int fd, const uint32_t *handles,
- uint64_t *points, uint32_t handle_count)
-{
- struct drm_syncobj_timeline_array args;
- int ret;
-
- memclear(args);
- args.handles = (uintptr_t)handles;
- args.points = (uintptr_t)points;
- args.count_handles = handle_count;
-
- ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL, &args);
- return ret;
-}
-
-drm_public int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
- unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled)
-{
- struct drm_syncobj_timeline_wait args;
- int ret;
-
- memclear(args);
- args.handles = (uintptr_t)handles;
- args.points = (uintptr_t)points;
- args.timeout_nsec = timeout_nsec;
- args.count_handles = num_handles;
- args.flags = flags;
-
- ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, &args);
- if (ret < 0)
- return -errno;
-
- if (first_signaled)
- *first_signaled = args.first_signaled;
- return ret;
-}
-
-
-drm_public int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
- uint32_t handle_count)
-{
- struct drm_syncobj_timeline_array args;
- int ret;
-
- memclear(args);
- args.handles = (uintptr_t)handles;
- args.points = (uintptr_t)points;
- args.count_handles = handle_count;
-
- ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_QUERY, &args);
- if (ret)
- return ret;
- return 0;
-}
-
-drm_public int drmSyncobjTransfer(int fd,
- uint32_t dst_handle, uint64_t dst_point,
- uint32_t src_handle, uint64_t src_point,
- uint32_t flags)
-{
- struct drm_syncobj_transfer args;
- int ret;
-
- memclear(args);
- args.src_handle = src_handle;
- args.dst_handle = dst_handle;
- args.src_point = src_point;
- args.dst_point = dst_point;
- args.flags = flags;
-
- ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TRANSFER, &args);
-
- return ret;
-}
diff --git a/xf86drm.h b/xf86drm.h
index 3fb1d1c..7773d71 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -733,7 +733,6 @@
extern int drmSetMaster(int fd);
extern int drmDropMaster(int fd);
-extern int drmIsMaster(int fd);
#define DRM_EVENT_CONTEXT_VERSION 4
@@ -876,18 +875,6 @@
uint32_t *first_signaled);
extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count);
extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count);
-extern int drmSyncobjTimelineSignal(int fd, const uint32_t *handles,
- uint64_t *points, uint32_t handle_count);
-extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
- unsigned num_handles,
- int64_t timeout_nsec, unsigned flags,
- uint32_t *first_signaled);
-extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
- uint32_t handle_count);
-extern int drmSyncobjTransfer(int fd,
- uint32_t dst_handle, uint64_t dst_point,
- uint32_t src_handle, uint64_t src_point,
- uint32_t flags);
#if defined(__cplusplus)
}
diff --git a/xf86drmHash.c b/xf86drmHash.c
index 2cf2b80..b2fa414 100644
--- a/xf86drmHash.c
+++ b/xf86drmHash.c
@@ -71,7 +71,6 @@
#include <stdio.h>
#include <stdlib.h>
-#include "libdrm_macros.h"
#include "xf86drm.h"
#include "xf86drmHash.h"
@@ -102,18 +101,24 @@
return hash;
}
-drm_public void *drmHashCreate(void)
+void *drmHashCreate(void)
{
HashTablePtr table;
+ int i;
table = drmMalloc(sizeof(*table));
if (!table) return NULL;
table->magic = HASH_MAGIC;
+ table->entries = 0;
+ table->hits = 0;
+ table->partials = 0;
+ table->misses = 0;
+ for (i = 0; i < HASH_SIZE; i++) table->buckets[i] = NULL;
return table;
}
-drm_public int drmHashDestroy(void *t)
+int drmHashDestroy(void *t)
{
HashTablePtr table = (HashTablePtr)t;
HashBucketPtr bucket;
@@ -164,7 +169,7 @@
return NULL;
}
-drm_public int drmHashLookup(void *t, unsigned long key, void **value)
+int drmHashLookup(void *t, unsigned long key, void **value)
{
HashTablePtr table = (HashTablePtr)t;
HashBucketPtr bucket;
@@ -177,7 +182,7 @@
return 0; /* Found */
}
-drm_public int drmHashInsert(void *t, unsigned long key, void *value)
+int drmHashInsert(void *t, unsigned long key, void *value)
{
HashTablePtr table = (HashTablePtr)t;
HashBucketPtr bucket;
@@ -196,7 +201,7 @@
return 0; /* Added to table */
}
-drm_public int drmHashDelete(void *t, unsigned long key)
+int drmHashDelete(void *t, unsigned long key)
{
HashTablePtr table = (HashTablePtr)t;
unsigned long hash;
@@ -213,7 +218,7 @@
return 0;
}
-drm_public int drmHashNext(void *t, unsigned long *key, void **value)
+int drmHashNext(void *t, unsigned long *key, void **value)
{
HashTablePtr table = (HashTablePtr)t;
@@ -230,7 +235,7 @@
return 0;
}
-drm_public int drmHashFirst(void *t, unsigned long *key, void **value)
+int drmHashFirst(void *t, unsigned long *key, void **value)
{
HashTablePtr table = (HashTablePtr)t;
diff --git a/xf86drmMode.c b/xf86drmMode.c
index 207d7be..b0ec609 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -48,7 +48,6 @@
#include <stdio.h>
#include <stdbool.h>
-#include "libdrm_macros.h"
#include "xf86drmMode.h"
#include "xf86drm.h"
#include <drm.h>
@@ -93,7 +92,7 @@
* A couple of free functions.
*/
-drm_public void drmModeFreeModeInfo(drmModeModeInfoPtr ptr)
+void drmModeFreeModeInfo(drmModeModeInfoPtr ptr)
{
if (!ptr)
return;
@@ -101,7 +100,7 @@
drmFree(ptr);
}
-drm_public void drmModeFreeResources(drmModeResPtr ptr)
+void drmModeFreeResources(drmModeResPtr ptr)
{
if (!ptr)
return;
@@ -113,7 +112,7 @@
drmFree(ptr);
}
-drm_public void drmModeFreeFB(drmModeFBPtr ptr)
+void drmModeFreeFB(drmModeFBPtr ptr)
{
if (!ptr)
return;
@@ -122,7 +121,7 @@
drmFree(ptr);
}
-drm_public void drmModeFreeCrtc(drmModeCrtcPtr ptr)
+void drmModeFreeCrtc(drmModeCrtcPtr ptr)
{
if (!ptr)
return;
@@ -130,7 +129,7 @@
drmFree(ptr);
}
-drm_public void drmModeFreeConnector(drmModeConnectorPtr ptr)
+void drmModeFreeConnector(drmModeConnectorPtr ptr)
{
if (!ptr)
return;
@@ -142,7 +141,7 @@
drmFree(ptr);
}
-drm_public void drmModeFreeEncoder(drmModeEncoderPtr ptr)
+void drmModeFreeEncoder(drmModeEncoderPtr ptr)
{
drmFree(ptr);
}
@@ -151,7 +150,7 @@
* ModeSetting functions.
*/
-drm_public drmModeResPtr drmModeGetResources(int fd)
+drmModeResPtr drmModeGetResources(int fd)
{
struct drm_mode_card_res res, counts;
drmModeResPtr r = 0;
@@ -245,10 +244,9 @@
return r;
}
-
-drm_public int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
- uint8_t bpp, uint32_t pitch, uint32_t bo_handle,
- uint32_t *buf_id)
+int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth,
+ uint8_t bpp, uint32_t pitch, uint32_t bo_handle,
+ uint32_t *buf_id)
{
struct drm_mode_fb_cmd f;
int ret;
@@ -268,10 +266,10 @@
return 0;
}
-drm_public int drmModeAddFB2WithModifiers(int fd, uint32_t width,
- uint32_t height, uint32_t pixel_format, const uint32_t bo_handles[4],
- const uint32_t pitches[4], const uint32_t offsets[4],
- const uint64_t modifier[4], uint32_t *buf_id, uint32_t flags)
+int drmModeAddFB2WithModifiers(int fd, uint32_t width, uint32_t height,
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
+ const uint64_t modifier[4], uint32_t *buf_id, uint32_t flags)
{
struct drm_mode_fb_cmd2 f;
int ret;
@@ -294,10 +292,10 @@
return 0;
}
-drm_public int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
- uint32_t pixel_format, const uint32_t bo_handles[4],
- const uint32_t pitches[4], const uint32_t offsets[4],
- uint32_t *buf_id, uint32_t flags)
+int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
+ uint32_t pixel_format, const uint32_t bo_handles[4],
+ const uint32_t pitches[4], const uint32_t offsets[4],
+ uint32_t *buf_id, uint32_t flags)
{
return drmModeAddFB2WithModifiers(fd, width, height,
pixel_format, bo_handles,
@@ -305,12 +303,12 @@
buf_id, flags);
}
-drm_public int drmModeRmFB(int fd, uint32_t bufferId)
+int drmModeRmFB(int fd, uint32_t bufferId)
{
return DRM_IOCTL(fd, DRM_IOCTL_MODE_RMFB, &bufferId);
}
-drm_public drmModeFBPtr drmModeGetFB(int fd, uint32_t buf)
+drmModeFBPtr drmModeGetFB(int fd, uint32_t buf)
{
struct drm_mode_fb_cmd info;
drmModeFBPtr r;
@@ -335,7 +333,7 @@
return r;
}
-drm_public int drmModeDirtyFB(int fd, uint32_t bufferId,
+int drmModeDirtyFB(int fd, uint32_t bufferId,
drmModeClipPtr clips, uint32_t num_clips)
{
struct drm_mode_fb_dirty_cmd dirty;
@@ -352,7 +350,7 @@
* Crtc functions
*/
-drm_public drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
+drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
{
struct drm_mode_crtc crtc;
drmModeCrtcPtr r;
@@ -384,7 +382,7 @@
return r;
}
-drm_public int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
+int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId,
uint32_t x, uint32_t y, uint32_t *connectors, int count,
drmModeModeInfoPtr mode)
{
@@ -409,8 +407,7 @@
* Cursor manipulation
*/
-drm_public int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle,
- uint32_t width, uint32_t height)
+int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height)
{
struct drm_mode_cursor arg;
@@ -424,9 +421,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg);
}
-drm_public int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle,
- uint32_t width, uint32_t height, int32_t hot_x,
- int32_t hot_y)
+int drmModeSetCursor2(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height, int32_t hot_x, int32_t hot_y)
{
struct drm_mode_cursor2 arg;
@@ -442,7 +437,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR2, &arg);
}
-drm_public int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y)
+int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y)
{
struct drm_mode_cursor arg;
@@ -458,7 +453,7 @@
/*
* Encoder get
*/
-drm_public drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id)
+drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id)
{
struct drm_mode_get_encoder enc;
drmModeEncoderPtr r = NULL;
@@ -590,17 +585,17 @@
return r;
}
-drm_public drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id)
+drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id)
{
return _drmModeGetConnector(fd, connector_id, 1);
}
-drm_public drmModeConnectorPtr drmModeGetConnectorCurrent(int fd, uint32_t connector_id)
+drmModeConnectorPtr drmModeGetConnectorCurrent(int fd, uint32_t connector_id)
{
return _drmModeGetConnector(fd, connector_id, 0);
}
-drm_public int drmModeAttachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info)
+int drmModeAttachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info)
{
struct drm_mode_mode_cmd res;
@@ -611,7 +606,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_ATTACHMODE, &res);
}
-drm_public int drmModeDetachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info)
+int drmModeDetachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info)
{
struct drm_mode_mode_cmd res;
@@ -622,7 +617,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_DETACHMODE, &res);
}
-drm_public drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id)
+drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id)
{
struct drm_mode_get_property prop;
drmModePropertyPtr r;
@@ -650,7 +645,7 @@
}
if (!(r = drmMalloc(sizeof(*r))))
- goto err_allocs;
+ return NULL;
r->prop_id = prop.prop_id;
r->count_values = prop.count_values;
@@ -676,7 +671,7 @@
return r;
}
-drm_public void drmModeFreeProperty(drmModePropertyPtr ptr)
+void drmModeFreeProperty(drmModePropertyPtr ptr)
{
if (!ptr)
return;
@@ -686,8 +681,7 @@
drmFree(ptr);
}
-drm_public drmModePropertyBlobPtr drmModeGetPropertyBlob(int fd,
- uint32_t blob_id)
+drmModePropertyBlobPtr drmModeGetPropertyBlob(int fd, uint32_t blob_id)
{
struct drm_mode_get_blob blob;
drmModePropertyBlobPtr r;
@@ -718,7 +712,7 @@
return r;
}
-drm_public void drmModeFreePropertyBlob(drmModePropertyBlobPtr ptr)
+void drmModeFreePropertyBlob(drmModePropertyBlobPtr ptr)
{
if (!ptr)
return;
@@ -727,9 +721,8 @@
drmFree(ptr);
}
-drm_public int drmModeConnectorSetProperty(int fd, uint32_t connector_id,
- uint32_t property_id,
- uint64_t value)
+int drmModeConnectorSetProperty(int fd, uint32_t connector_id, uint32_t property_id,
+ uint64_t value)
{
struct drm_mode_connector_set_property osp;
@@ -747,7 +740,7 @@
* -EINVAL or invalid bus id
* -ENOSYS if no modesetting support
*/
-drm_public int drmCheckModesettingSupported(const char *busid)
+int drmCheckModesettingSupported(const char *busid)
{
#if defined (__linux__)
char pci_dev_dir[1024];
@@ -855,9 +848,8 @@
return -ENOSYS;
}
-drm_public int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size,
- uint16_t *red, uint16_t *green,
- uint16_t *blue)
+int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size,
+ uint16_t *red, uint16_t *green, uint16_t *blue)
{
struct drm_mode_crtc_lut l;
@@ -871,9 +863,8 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_GETGAMMA, &l);
}
-drm_public int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size,
- uint16_t *red, uint16_t *green,
- uint16_t *blue)
+int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size,
+ uint16_t *red, uint16_t *green, uint16_t *blue)
{
struct drm_mode_crtc_lut l;
@@ -887,7 +878,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETGAMMA, &l);
}
-drm_public int drmHandleEvent(int fd, drmEventContextPtr evctx)
+int drmHandleEvent(int fd, drmEventContextPtr evctx)
{
char buffer[1024];
int len, i;
@@ -955,7 +946,7 @@
return 0;
}
-drm_public int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id,
+int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id,
uint32_t flags, void *user_data)
{
struct drm_mode_crtc_page_flip flip;
@@ -969,7 +960,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_PAGE_FLIP, &flip);
}
-drm_public int drmModePageFlipTarget(int fd, uint32_t crtc_id, uint32_t fb_id,
+int drmModePageFlipTarget(int fd, uint32_t crtc_id, uint32_t fb_id,
uint32_t flags, void *user_data,
uint32_t target_vblank)
{
@@ -985,7 +976,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_PAGE_FLIP, &flip_target);
}
-drm_public int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id,
+int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id,
uint32_t fb_id, uint32_t flags,
int32_t crtc_x, int32_t crtc_y,
uint32_t crtc_w, uint32_t crtc_h,
@@ -1011,7 +1002,7 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETPLANE, &s);
}
-drm_public drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id)
+drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id)
{
struct drm_mode_get_plane ovr, counts;
drmModePlanePtr r = 0;
@@ -1062,7 +1053,7 @@
return r;
}
-drm_public void drmModeFreePlane(drmModePlanePtr ptr)
+void drmModeFreePlane(drmModePlanePtr ptr)
{
if (!ptr)
return;
@@ -1071,7 +1062,7 @@
drmFree(ptr);
}
-drm_public drmModePlaneResPtr drmModeGetPlaneResources(int fd)
+drmModePlaneResPtr drmModeGetPlaneResources(int fd)
{
struct drm_mode_get_plane_res res, counts;
drmModePlaneResPtr r = 0;
@@ -1116,7 +1107,7 @@
return r;
}
-drm_public void drmModeFreePlaneResources(drmModePlaneResPtr ptr)
+void drmModeFreePlaneResources(drmModePlaneResPtr ptr)
{
if (!ptr)
return;
@@ -1125,7 +1116,7 @@
drmFree(ptr);
}
-drm_public drmModeObjectPropertiesPtr drmModeObjectGetProperties(int fd,
+drmModeObjectPropertiesPtr drmModeObjectGetProperties(int fd,
uint32_t object_id,
uint32_t object_type)
{
@@ -1186,7 +1177,7 @@
return ret;
}
-drm_public void drmModeFreeObjectProperties(drmModeObjectPropertiesPtr ptr)
+void drmModeFreeObjectProperties(drmModeObjectPropertiesPtr ptr)
{
if (!ptr)
return;
@@ -1195,7 +1186,7 @@
drmFree(ptr);
}
-drm_public int drmModeObjectSetProperty(int fd, uint32_t object_id, uint32_t object_type,
+int drmModeObjectSetProperty(int fd, uint32_t object_id, uint32_t object_type,
uint32_t property_id, uint64_t value)
{
struct drm_mode_obj_set_property prop;
@@ -1223,7 +1214,7 @@
drmModeAtomicReqItemPtr items;
};
-drm_public drmModeAtomicReqPtr drmModeAtomicAlloc(void)
+drmModeAtomicReqPtr drmModeAtomicAlloc(void)
{
drmModeAtomicReqPtr req;
@@ -1238,7 +1229,7 @@
return req;
}
-drm_public drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr old)
+drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr old)
{
drmModeAtomicReqPtr new;
@@ -1267,8 +1258,7 @@
return new;
}
-drm_public int drmModeAtomicMerge(drmModeAtomicReqPtr base,
- drmModeAtomicReqPtr augment)
+int drmModeAtomicMerge(drmModeAtomicReqPtr base, drmModeAtomicReqPtr augment)
{
if (!base)
return -EINVAL;
@@ -1297,23 +1287,23 @@
return 0;
}
-drm_public int drmModeAtomicGetCursor(drmModeAtomicReqPtr req)
+int drmModeAtomicGetCursor(drmModeAtomicReqPtr req)
{
if (!req)
return -EINVAL;
return req->cursor;
}
-drm_public void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor)
+void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor)
{
if (req)
req->cursor = cursor;
}
-drm_public int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
- uint32_t object_id,
- uint32_t property_id,
- uint64_t value)
+int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
+ uint32_t object_id,
+ uint32_t property_id,
+ uint64_t value)
{
if (!req)
return -EINVAL;
@@ -1342,7 +1332,7 @@
return req->cursor;
}
-drm_public void drmModeAtomicFree(drmModeAtomicReqPtr req)
+void drmModeAtomicFree(drmModeAtomicReqPtr req)
{
if (!req)
return;
@@ -1365,8 +1355,8 @@
return second->property_id - first->property_id;
}
-drm_public int drmModeAtomicCommit(int fd, drmModeAtomicReqPtr req,
- uint32_t flags, void *user_data)
+int drmModeAtomicCommit(int fd, drmModeAtomicReqPtr req, uint32_t flags,
+ void *user_data)
{
drmModeAtomicReqPtr sorted;
struct drm_mode_atomic atomic;
@@ -1470,9 +1460,8 @@
return ret;
}
-drm_public int
-drmModeCreatePropertyBlob(int fd, const void *data, size_t length,
- uint32_t *id)
+int
+drmModeCreatePropertyBlob(int fd, const void *data, size_t length, uint32_t *id)
{
struct drm_mode_create_blob create;
int ret;
@@ -1495,7 +1484,7 @@
return 0;
}
-drm_public int
+int
drmModeDestroyPropertyBlob(int fd, uint32_t id)
{
struct drm_mode_destroy_blob destroy;
@@ -1505,9 +1494,8 @@
return DRM_IOCTL(fd, DRM_IOCTL_MODE_DESTROYPROPBLOB, &destroy);
}
-drm_public int
-drmModeCreateLease(int fd, const uint32_t *objects, int num_objects, int flags,
- uint32_t *lessee_id)
+int
+drmModeCreateLease(int fd, const uint32_t *objects, int num_objects, int flags, uint32_t *lessee_id)
{
struct drm_mode_create_lease create;
int ret;
@@ -1525,7 +1513,7 @@
return -errno;
}
-drm_public drmModeLesseeListPtr
+drmModeLesseeListPtr
drmModeListLessees(int fd)
{
struct drm_mode_list_lessees list;
@@ -1552,7 +1540,7 @@
return ret;
}
-drm_public drmModeObjectListPtr
+drmModeObjectListPtr
drmModeGetLease(int fd)
{
struct drm_mode_get_lease get;
@@ -1579,7 +1567,7 @@
return ret;
}
-drm_public int
+int
drmModeRevokeLease(int fd, uint32_t lessee_id)
{
struct drm_mode_revoke_lease revoke;
diff --git a/xf86drmMode.h b/xf86drmMode.h
index a32902f..3cd27ae 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -49,12 +49,12 @@
* header defining uint32_t, int32_t and uint16_t.
*
* It aims to provide a randr1.2 compatible interface for modesettings in the
- * kernel, the interface is also meant to be used by libraries like EGL.
+ * kernel, the interface is also ment to be used by libraries like EGL.
*
* More information can be found in randrproto.txt which can be found here:
* http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git
*
- * There are some major differences to be noted. Unlike the randr1.2 proto you
+ * There are some major diffrences to be noted. Unlike the randr1.2 proto you
* need to create the memory object of the framebuffer yourself with the ttm
* buffer object interface. This object needs to be pinned.
*/
@@ -348,7 +348,7 @@
extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr);
/**
- * Retrieves all of the resources associated with a card.
+ * Retrives all of the resources associated with a card.
*/
extern drmModeResPtr drmModeGetResources(int fd);
@@ -357,7 +357,7 @@
*/
/**
- * Retrieve information about framebuffer bufferId
+ * Retrive information about framebuffer bufferId
*/
extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId);
@@ -397,7 +397,7 @@
*/
/**
- * Retrieve information about the ctrt crtcId
+ * Retrive information about the ctrt crtcId
*/
extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId);
diff --git a/xf86drmRandom.c b/xf86drmRandom.c
index 51e9676..81f0301 100644
--- a/xf86drmRandom.c
+++ b/xf86drmRandom.c
@@ -74,13 +74,12 @@
#include <stdio.h>
#include <stdlib.h>
-#include "libdrm_macros.h"
#include "xf86drm.h"
#include "xf86drmRandom.h"
#define RANDOM_MAGIC 0xfeedbeef
-drm_public void *drmRandomCreate(unsigned long seed)
+void *drmRandomCreate(unsigned long seed)
{
RandomState *state;
@@ -110,13 +109,13 @@
return state;
}
-drm_public int drmRandomDestroy(void *state)
+int drmRandomDestroy(void *state)
{
drmFree(state);
return 0;
}
-drm_public unsigned long drmRandom(void *state)
+unsigned long drmRandom(void *state)
{
RandomState *s = (RandomState *)state;
unsigned long hi;
@@ -130,7 +129,7 @@
return s->seed;
}
-drm_public double drmRandomDouble(void *state)
+double drmRandomDouble(void *state)
{
RandomState *s = (RandomState *)state;
diff --git a/xf86drmSL.c b/xf86drmSL.c
index 3826df9..a12fa1d 100644
--- a/xf86drmSL.c
+++ b/xf86drmSL.c
@@ -41,7 +41,6 @@
#include <stdio.h>
#include <stdlib.h>
-#include "libdrm_macros.h"
#include "xf86drm.h"
#define SL_LIST_MAGIC 0xfacade00LU
@@ -98,7 +97,7 @@
return level;
}
-drm_public void *drmSLCreate(void)
+void *drmSLCreate(void)
{
SkipListPtr list;
int i;
@@ -115,7 +114,7 @@
return list;
}
-drm_public int drmSLDestroy(void *l)
+int drmSLDestroy(void *l)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr entry;
@@ -152,7 +151,7 @@
return entry->forward[0];
}
-drm_public int drmSLInsert(void *l, unsigned long key, void *value)
+int drmSLInsert(void *l, unsigned long key, void *value)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr entry;
@@ -185,7 +184,7 @@
return 0; /* Added to table */
}
-drm_public int drmSLDelete(void *l, unsigned long key)
+int drmSLDelete(void *l, unsigned long key)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr update[SL_MAX_LEVEL + 1];
@@ -212,7 +211,7 @@
return 0;
}
-drm_public int drmSLLookup(void *l, unsigned long key, void **value)
+int drmSLLookup(void *l, unsigned long key, void **value)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr update[SL_MAX_LEVEL + 1];
@@ -228,9 +227,9 @@
return -1;
}
-drm_public int drmSLLookupNeighbors(void *l, unsigned long key,
- unsigned long *prev_key, void **prev_value,
- unsigned long *next_key, void **next_value)
+int drmSLLookupNeighbors(void *l, unsigned long key,
+ unsigned long *prev_key, void **prev_value,
+ unsigned long *next_key, void **next_value)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr update[SL_MAX_LEVEL + 1] = {0};
@@ -254,7 +253,7 @@
return retcode;
}
-drm_public int drmSLNext(void *l, unsigned long *key, void **value)
+int drmSLNext(void *l, unsigned long *key, void **value)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr entry;
@@ -273,7 +272,7 @@
return 0;
}
-drm_public int drmSLFirst(void *l, unsigned long *key, void **value)
+int drmSLFirst(void *l, unsigned long *key, void **value)
{
SkipListPtr list = (SkipListPtr)l;
@@ -284,7 +283,7 @@
}
/* Dump internal data structures for debugging. */
-drm_public void drmSLDump(void *l)
+void drmSLDump(void *l)
{
SkipListPtr list = (SkipListPtr)l;
SLEntryPtr entry;