Flush cache by VA on aarch64
On aarch64, GBL flushes data cache by all sets/ways. This is only valid
however, during core power-up/power-down sequence and does not guarantee
to work outside of it, i.e. in smp mode. The more reliable approach is
to flush by VA, i.e. "dc civac", which guarantees reaching PoC. The CL
switches to use `flush_dcache_range` from the ATF library and explicitly
flushes only the image buffers needed for kernel booting. The rest of
the memory, in particular the stack, is left stale and the kernel jump
logic is reworked to only use register values loaded before disabling
MMU/cache.
Bug: 316349883
Change-Id: I6bc67c562bd3a384879d23bd11344d03d9ee2379
5 files changed