| commit | d110852513148a7ec44fad4e036455aeb816d713 | [log] [tgz] |
|---|---|---|
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | Tue Nov 02 17:30:46 2010 +0800 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Tue Nov 02 10:05:46 2010 +0000 |
| tree | 5c72fa12fa653804a4d13658a641a713d6849acd | |
| parent | 328fc1325f144027f4a8269b11e9f8dcf1edcb97 [diff] |
agp/intel: fix cache control for sandybridge This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3. Let's set the correct bit for LLC+MLC and LLC only. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>