commit 598acab44dcbda0e300d9d080e81566334138e7d
author Michal Simek <monstr@monstr.eu> Mon Apr 26 13:43:23 2010 +0200
committer Michal Simek <monstr@monstr.eu> Thu May 06 11:21:59 2010 +0200
tree 19f8a929ce264068a21b25b91258afe4bad64b75
parent 77543cebab7387eab7d482e90018a64d6f2ced1e

microblaze: Define correct L1_CACHE_SHIFT value

Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>

arch/microblaze/include/asm/cache.h

diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h
index e522108..4efe96a 100644
--- a/arch/microblaze/include/asm/cache.h
+++ b/arch/microblaze/include/asm/cache.h
@@ -15,7 +15,7 @@
 
 #include <asm/registers.h>
 
-#define L1_CACHE_SHIFT	2
+#define L1_CACHE_SHIFT 5
 /* word-granular cache in microblaze */
 #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)