| commit | 3cd049ab9edd48a41955b8d05f0bc57ead918456 | [log] [tgz] |
|---|---|---|
| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | Thu Sep 01 15:44:42 2016 +0530 |
| committer | Bjorn Helgaas <bhelgaas@google.com> | Tue Sep 13 10:38:19 2016 -0500 |
| tree | 8c02857a2f569c5a83e97f5626242b8185d97178 | |
| parent | b584fa1fde71aa57fb63d32f66ff6c192ff7f2c5 [diff] |
PCI: xilinx: Clear interrupt register for invalid interrupt The interrupt decode register is not being cleared if an invalid interrupt arises. Clear the decode register in this case. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Michal Simek <michal.simek@xilinx.com>