| commit | 1fc870c7efa364862c3bc792cfbdb38afea26742 | [log] [tgz] |
|---|---|---|
| author | Olav Haugan <ohaugan@codeaurora.org> | Mon Aug 04 19:01:02 2014 +0100 |
| committer | Will Deacon <will.deacon@arm.com> | Mon Sep 01 16:48:56 2014 +0100 |
| tree | 1c5719e57b7fccba898486eb622027036ee770a2 | |
| parent | a18037b27ebd23edf5edad8bc6ceb72e4bb5716d [diff] |
iommu/arm-smmu: fix programming of SMMU_CBn_TCR for stage 1 Stage-1 context banks do not have the SMMU_CBn_TCR[SL0] field since it is only applicable to stage-2 context banks. This patch ensures that we don't set the reserved TCR bits for stage-1 translations. Cc: <stable@vger.kernel.org> Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>